Design and implementation of a power transistor temperature measurement circuit for a multilevel active-clamped power converter

Semiconductor power switches are largely considered the most fragile components in power electronic converters. In order to increase the reliability of power devices, it is important to avoid high junction temperatures and high junction temperature fluctuations, which are basically caused by conduction and switching losses in the devices. The purpose of the thesis is to find and implement a robust method to sense the junction temperature of a power switch and deliver this information to the converter controller. The method will be implemented using a circuit that has to be small, cheap and with low-power consumption, since the circuit will be fed by the same power supply used by the gate-driver circuit of the power device. This method is designed to be applied into the multilevel active-clamped converter. One of the main advantages of this topology is its degree of freedom to select the power switch that concentrates the switching losses in the switching-state transitions. By sensing the switches temperatures, it will be possible to always select the coolest transistor to take the switching losses. This will enable a better distribution of the temperature and a lower cost of the cooling system. In addition to this, an improved reliability of the system can be achieved.Incomin

Models and methods for the design of isolated power converters in high-frequency high-efficiency applications

2011 - 2012Isolated power supplies design requires the achievement of overall stress, losses, cost, size and reliability trade-off. This problem is of considerable importance in modern applications of power converters, as for energy saving issues as for the achievement of high power density capabilities needed to integrate the power supply into the same boards where the system they feed is hosted. The aim of this PhD dissertation is to discuss the fundamental issues regarding the design of high-efficiency high-power-density isolated power converters, related to the transformers design and to the system-level analysis of functional and parametric correlations existing among transformers and silicon devices in the achievement of high efficiency. Transformer design is the central issue in isolated switching power supplies design. Affording a preliminary reliable investigation of possible feasible power supply designs using off-the-shelf transformers can be of great help in reducing the time to prototyping and the time-to-market. Even though many off-the-shelf transformers are available today for standard applications, many special situations occur such that the design of a custom transformer is required. New design method are needed in order to enable a wider detection and investigation of possible transformer design solutions by means of a straightforward matching between the available magnetic cores, the operating conditions of the transformer to be designed and the design constraints to be fulfilled. A critical re-examination of transformers design methods discussed in technical literature has been afforded to highlighting some common misleading assumptions which can hinder the minimization of the transformer. Thus, a new design approach has been investigated and discussed, which helps in easily identifying possible transformer solutions in critical custom designs for a given application, complying with losses and size constraints. The new method is aimed at quickly identifying possible combinations of magnetic cores and windings turns number when many possible design might be feasible and a fast comparative evaluation is needed for preliminary cores selection. Novel geometric form factors of magnetic core (Kf and Kc) have been introduced and a consequent classification procedure for magnetic cores has been obtained, showing the correlation between the characteristics of the core and the specific applications in which each type of core offers major advantages in terms of minimizing losses and/or size. A magneto-electro-thermal macro model of the transformer has been adopted in order to investigate the dependency of total transformer losses on the temperature and to analyze the temperature sensitivity of form factor constraints of magnetic cores for power loss compliance. In particular, temperature-dependent boundaries curves both for the core window area and cross-section and for the form factors Kf and Kc have been obtained, allowing quick identification of feasible design solutions, complying with all design constraints, included thermal issues. Transformers and silicon devices do inextricably share the responsibility of major losses in isolated power supplies, and the optimization of the former normally impinges the one of the latter. As a consequence, the intimate correlation among these parts need to be jointly considered regarding the way the characteristics of one device influence the losses of the other one. In order to achieve reliable comparative evaluations among different design set-up, a new versatile numerical model for commutations analysis of power MOSFETs has been developed. The model takes into account the non-linear behavior of the inter-electrode capacitances and has been conceived to work as with parameters and information contained in the devices datasheets as with more detailed models. A Modified Forward Euler (MFE) numerical technique has been specifically developed and adopted in the realization of a numerical algorithm which solves the non linear system of differential equations describing the effect of parasitic capacitances in whatever operating conditions, in order to overcome the limitation exhibited by ODEs techniques for stiff problems in this particular application. The new MFE technique allows to compare the switching characteristics of MOSFETs with a good level of reliability and to obtain a detailed analysis of capacitive currents paths circulating between MOSFETs in half-bridge configuration during commutations. The numerical device-level model of the MOSFETs couples has been first tested in the analysis of basic non isolated synchronous rectification buck converter and then used into an integrated model allowing the analysis of Active Clamp Forward converters. It has been also demonstrated that the model adopted for the switching cell can be implemented in circuit simulators like Micro-Cap. The correlations existing between the parasitic parameters which characterize both transformer and MOSFETs and their impact on the switching behavior and the efficiency of such a conversion system can be effectively investigated by using such modeling approach, thus overcoming the limitations and unreliability of simplified analytical formulas for the prediction of the ZVS achievement. In particular, the integrated system model has been successfully used to determine the mutual constraint conditions between magnetic devices and solid state devices to achieve soft-switching, and their effects on the physical feasibility and design/selection of such power devices in order to achieve high efficiency. Experimental activities have been done to validate the methods and models proposed, through the implementation of on-line losses measurements techniques for both magnetic and solid state devices. The high switching frequency, high slew rates, high current and low leakage devices make such measures extremely sensitive to the parasitic circuit layout parameters. In order to achieve reliable measurements, non-conventional measurement techniques have been investigated based on the use of current sensing MOSFETs, and applied in the development and implementation of new measuring circuits. [edited by author]XI n.s

Advanced wound-rotor machine model with saturation and high-frequency effects

Nowadays, the doubly–fed induction generator (DFIG) is perhaps the most common type of generator used in onshore wind turbines. With the thriving development of wind energy, there is a high demand for precisely predicting the dynamic performance of the DFIG. Due to the involvement of power electronics, massive high–frequency harmonics are injected into the machine leading to high–frequency effects such as parasitic currents. As the core of DFIGs, the wound–rotor induction machine must be well modeled to capture these significant phenomena in the operation of wind turbines. However, the T–equivalent model, which is currently the most widely used model in machine dynamic studies and controller designs, is incapable to simulate machine behaviors in the high–frequency range. The aim of this research is to develop a novel model of a wound–rotor induction machine, which incorporates magnetic saturation of the main flux path and high–frequency effects. The model’s experimental parameterization procedure is described in detail. This consists of standstill frequency response tests, and a test for determining the machine’s magnetizing characteristic and turns ratio. Time–domain simulations are used to highlight the capabilities of the proposed model, and to compare its predictions with those of a classical model at both transient and steady states. The results show that the proposed model can better capture the dynamic performance with the consideration of magnetic saturation. What is more, the high–frequency current ripples, which are caused by common–mode ground currents can also be simulated in the proposed model

Caractérisation et modélisation électro-thermique distribuée d'une puce IGBT : Application aux effets du vieillissement de la métallisation d'émetteur

Power modules, organized around power chips (IGBT, MOSFET, diodes, …), are increasingly needed for transportations systems such a rail, aeronautics and automobile. In all these application, power devices reliability is still a critical point. This is particularly the case in the powertrain of hybrid or electric vehicle in which power chips are often subjected to very high electrical and thermal stress levels such as hybrid or electric vehicle, power devices are subjected to very high electrical, thermal and mechanical stress levels which may affect their reliability.Thus, the ability to analyze the coupled phenomena and to accurately predict degradation mechanisms in power semiconductors and their effects due to electro-thermal and thermo-mechanical stress is essential. Especially on the semiconductor chip where significant physical interactions occur and its immediate vicinity. The aim of this work is to highlight the electro-mechanical and thermal stress and their effects on the semiconductor chip and its immediate vicinity, by evaluating the effects of damage using distributed models. This work consists of two parts :An original experimental approach concerning the elctro-thermal characterization of cross section power chips (IGBT and diodes). In this approach, it is exposed for the first time, an original way to characterize vertical thermal distributions inside high power silicon devices under forward bias. Thus, the vertical mapping of temperature and mechanical stress of IGBT and diode chip are presented. The impact of this work that is opens a wide field of investigations in high power semiconductor devices. The second part is theoretical and aims to implementing a distributed electro-thermal model of IGBT chip.The modeling strategy consists on a discretization of the power semiconductor chip in macro-cells with a distributed electro-thermal behavior over the chip area. In case of the IGBT devices each macro-cell is governed by the Hefner model and electrically linked by their terminals. Temperature variable used in these macro-cells are obtained by a nodal 3D-RC thermal model. This allows the distributed electro-thermal problem to be solved homogeneously and simultaneously by a circuit solver such as Simplorer. The aim of this model is to allow the accurate analysis of some effects ine the electrical and thermal coupling over the chip. Especially, this model should allow explaining some effects such as the contacts position over the die metallization and the ageing of the emitter metallization of the chip. In a first step, the model is used to clarify how the current and the temperature map are distributed over the chip according to the relative positions between cells and wire bond contacts on the top-metal during short-circuit operation. In a second step, we will show how dynamic latch-up failures may occur when trying to turn-off a short circuit process.Les convertisseurs de puissance structurés autour de puces de puissance (IGBT, MOSFET, diodes, ...) sont de plus en plus sollicités dans les systèmes de transport, du ferroviaire à l'aéronautique, en passant par l'automobile. Dans toutes ces applications, la fiabilité des composants constitue encore un point critique. C'est notamment le cas dans la chaîne de traction de véhicules électriques (VE) et hybrides (VH, où les puces sont souvent exposées à de fortes contraintes électriques, thermiques et mécaniques pouvant conduire à la défaillance. Dans ce contexte, l'amélioration des connaissances sur les effets des dégradations des composants semi-conducteurs de puissance et leurs assemblages dus au stress électrothermiques et thermomécaniques est incontournable. En particulier sur la puce semi-conductrice elle-même, siège d'interactions physiques importantes, et en son voisinage immédiat. Les objectifs de la thèse sont de mettre en lumière les stress électro-thermiques et mécaniques dans les puces et leurs effets sur la puce et son voisinage immédiat et à évaluer les effets de dégradations à l'aide de modèles distribués. Les travaux comportent ainsi deux volets. Un volet expérimental original visant la caractérisation électrothermique de puce de puissance (IGBT et diode) sur la base de micro-sections. La piste suivie par cette approche devrait permettre de rendre possible la caractérisation d'un certain nombre de grandeurs physiques (thermiques, électriques et mécaniques) sur les tranches sectionnées des puces sous polarisation (en statique, voire en dynamique) et ainsi contribuer à l'amélioration des connaissances de leur comportement. Ainsi, des cartographies de distributions verticales de température de puce IGBT et diode et de contraintes mécaniques sont présentées. C'est à notre connaissance une voie originale qui devrait permettre de d’ouvrir un large champ d'investigation dans le domaine de la puissance.Le second volet est théorique et consiste à mettre en place un modèle électrothermique distribué de puce IGBT. Cette modélisation comme nous l'envisageons implique de coupler dans un unique environnement (Simplorer) une composante thermique et une composant électrique. Le développement choisi passe par l'utilisation de modèle physique d'IGBT tels que celui de Hefner. Ce modèle est ensuite appliqué pour étudier le rôle et les effets du vieillissement de la métallisation de puce lors de régimes électriques extrêmes répétitifs tels que les courts-circuits. Un aspect original du travail est la démonstration par analyse numérique du mode de défaillance par latch-up dynamique à l'instant de la commande d'ouverture du courant de court-circuit. Ce phénomène bien qu'ayant été observé lors de vieillissement d'IGBT par répétition de courts-circuits n'avait à notre connaissance pas encore été simulé. La modélisation distribuée de la puce et la simulation du phénomène nous a ainsi permis de vérifier certaines hypothèses

Millimeter-wave GaN high electron mobility transistors and their integration with silicon electronics

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references.In spite of the great progress in performance achieved during the last few years, GaN high electron mobility transistors (HEMTs) still have several important issues to be solved for millimeter-wave (30 ~ 300 GHz) applications. One of the key challenges is to improve its high frequency characteristics. In this thesis, we particularly focus on fT and fma, two of the most important figures of merit in frequency performance of GaN HEMTs and investigate them both analytically and experimentally. Based on an improved physical understanding and new process technologies, we aim to demonstrate the state-of-the-art high frequency performance of GaN HEMTs. To maximize fmax, parasitic components in the device (Ri, R, Rg, Cgd, and go) are carefully minimized and the optimized 60-nm AlGaN/GaN HEMT shows a very high fmax of 300 GHz. The lower-than-expected fT observed in many AlGaN/GaN HEMTs is attributed to a significant drop of the intrinsic transconductance at high frequency (RF gm) with respect to the intrinsic DC g. (called RF gm-collapse). By suppressing RF gm-collapse and harmoniously scaling the device, a record fT of 225 GHz is achieved in the 55-nm AlGaN/GaN HEMT. Another important challenge for the wide adoption of GaN devices is to develop suitable technology to integrate these GaN transistors with Si(100) electronics. In this thesis, we demonstrate a new technology to integrate, for the first time, GaN HEMTs and Si(100) MOSFETs on the same chip. This integration enables the development of hybrid circuits that take advantage of the high-frequency and power capability of GaN and the unsurpassed circuit scalability and complexity of Si electronics.by Jinwook W. Chung.Ph.D

Multilevel harmonic balance analysis of large-scale nonlinear RF circuits via Newton-Krylov and tensor-Krylov methods

Orientador: Hugo Enrique Hernandez FigueroaTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de ComputaçãoResumo: Este trabalho, tem como objetivo o desenvolvimento de novas técnicas, para análise de regime permanente não-autonoma de circuitos de alta-velocidade não-lineares em grande-escala. Para tal, é proposto um novo método do balanço harmônico (BH) fundamentado em uma eficiente metodologia de decomposição multi-níveis, que subdivide um circuito não-linear em grande escala em uma estrutura hierarquica de super-redes (SuRs) esparsamente interconectadas. Mais precisamente, em cada nível de hierarquia, o circuito é composto por SuRs intermediárias, SuRs de fundo, e redes de conexão (RCs). As SuRs de fundo são decompostas em um aglomerado de subredes não-lineares (SRNs) correspondendo a dispositivos semicondutores, que por sua vez, estão envolvidos por uma sub-rede linear (SRL). A equação de estado e de sonda das SuRs de fundo foram obtidas utilizando uma nova metodologia que combina a formulação de espaço de estado (FEE) para as SRNs com a formulação nodal modificada (FNM) para a SRL. Esta metodologia FEE/FNM produz um sistema quadrado de equações com menor tamanho possível. Para realização das conversões do sinal entre os domínios do tempo e da frequência, foram discutidas e implementadas diferentes transformadas de Fourier discreta (TFDs), para operação em regime multi-tons, incluindo sinais com modulação digital. A equação determinante do BH multi-níveis do circuito assume uma estrutura hierarquica do tipo bloco diagonal com borda , que pode ser eficientemente resolvida utilizando técnicas de processamento paralelo. A matriz jacobiana de cada SuR de fundo é processada utilizando eficientes técnicas de matrizes esparsas, junto com o conceito de espectro de derivada. Para a solução da equação determinante, foram utilizados os métodos de Newton e do tensor para problemas de pequena- e média-escala, e os métodos de Newton inexato e do tensor inexato para problemas em grande-escala. A globalização via pesquisa-em-linha com retrocedimento, foi adotada para nestes solucionadores não-lineares. Entretanto, para o método do tensor e do tensor inexato, também foi adotada a técnica de pesquisa-em-linha curvilinear. Nos métodos inexatos, técnicas de pré-condicionamento foram utilizadas, para aumentar a eficiência e a robustez do solucionador linear iterativo em subespaço de Krylov (GMRES, GMRES-Bt e TGMRES-Bt). Finalmente, a formulação proposta foi validada e a eficiência do método do tensor e do tensor inexato comparada com o método de Newton e de Newton inexato, para diferentes topologias de circuitos utilizando diodos, FETs e HBTs, e operando sob diferentes regimes de excitação multi-tons.Abstract: This work deals with the development of new techniques for nonautonomous nonlinear steady-state analysis of high-speed large-scale integrated circuits. To this end, it is proposed a novel harmonic balance (HB) method fundamented on a efficient multi-level decomposition methodology, that divides a large-scale circuit into hierarchical structure of sparsely interconnected supernetworks (SuNs). More precisely, the circuit is composed by intermediary SuRs, bottom SuRs and connection networks (CNs). The bottom SuNs are decomposed into a cluster of nonlinear subnetworks (NSNs) corresponding to the opto-electronic semiconductor devices, which in turn, are embedded by a linear subnetwork (LSN). Multi-port elements can be included in the LSN, in order to use measured data or results from electromagnetic analysis of structures with complex geometries. The formulation of the bottom SuN state and probe equations uses an improved table-oriented statespace formulation (SSF), that produces a square system with the lowest possible size, which is equal to the number of nonlinear state-variables (branch voltages and currents) that act as argument of the fuctions representing the semiconductor devices nonlinearities. The SSF is compared with the classical modified nodal formulation (MNF). For dealing with signal timefrequency conversions, discrete Fourier transform (DFT) techniques for different multi-tone regimes are discussed, including complex digitally modulated signals. The multi-level HB determining equation of the circuit assumes a hierarchical block bordered structure that can be efficiently tackled by parallel processing techniques. The HB jacobian matrix is handled using efficient sparse matrix techniques with a proper definition of the derivatives spectra. For the solution of a large-size HB problem, we investigated the applications of inexact tensor method based on Krylov-subspace techniques. Preconditioning are used to improve the robustness of the iterative tensor solver. To determine the circuit DC regime, we employ the tensor method. We adopted the backtracking linesearch technique as a globalisation strategy. However, for the tensor method, in particular, a curvilinear linesearch was also implemented. Finally, the formulation was validated and, the tensor and inexact tensor method efficiency was compared with the Newton and inexact Newton method, respectively, for several different circuits using diodos, FETs and HBTs, and operating under different multi-tone regimes.DoutoradoEngenharia de TelecomunicaçõesDoutor em Engenharia Elétric

NASA patent abstracts bibliography: A continuing bibliography. Section 2: Indexes (supplement 18)

Entries for 3900 patents and patent applications citations for the period May 1980 through December 1980 are listed. Indexes for subject, invention, source, number, and accession number are included

Applications of MATLAB in Science and Engineering

The book consists of 24 chapters illustrating a wide range of areas where MATLAB tools are applied. These areas include mathematics, physics, chemistry and chemical engineering, mechanical engineering, biological (molecular biology) and medical sciences, communication and control systems, digital signal, image and video processing, system modeling and simulation. Many interesting problems have been included throughout the book, and its contents will be beneficial for students and professionals in wide areas of interest

Unmanned Aircraft Systems in the Cyber Domain

Unmanned Aircraft Systems are an integral part of the US national critical infrastructure. The authors have endeavored to bring a breadth and quality of information to the reader that is unparalleled in the unclassified sphere. This textbook will fully immerse and engage the reader / student in the cyber-security considerations of this rapidly emerging technology that we know as unmanned aircraft systems (UAS). The first edition topics covered National Airspace (NAS) policy issues, information security (INFOSEC), UAS vulnerabilities in key systems (Sense and Avoid / SCADA), navigation and collision avoidance systems, stealth design, intelligence, surveillance and reconnaissance (ISR) platforms; weapons systems security; electronic warfare considerations; data-links, jamming, operational vulnerabilities and still-emerging political scenarios that affect US military / commercial decisions. This second edition discusses state-of-the-art technology issues facing US UAS designers. It focuses on counter unmanned aircraft systems (C-UAS) – especially research designed to mitigate and terminate threats by SWARMS. Topics include high-altitude platforms (HAPS) for wireless communications; C-UAS and large scale threats; acoustic countermeasures against SWARMS and building an Identify Friend or Foe (IFF) acoustic library; updates to the legal / regulatory landscape; UAS proliferation along the Chinese New Silk Road Sea / Land routes; and ethics in this new age of autonomous systems and artificial intelligence (AI).https://newprairiepress.org/ebooks/1027/thumbnail.jp

Near hybrid passenger vehicle development program, phase 1. Appendices C and D, Volume 2

Results of tradeoff studies are presented in summary form. Various aspects of the overall vehicle design discussed include selection of the base vehicle, the battery pack configuration, structural modifications, occupant protection, vehicle dynamics, and aerodynamics. The drivetrain design and integration, power conditioning unit, battery subsystem, control system, environmental system are described. Specifications, weight breakdown, and energy consumption measures, and advanced technology components are included