A maximum density rule for surfaces of quasicrystals

A rule due to Bravais of wide validity for crystals is that their surfaces correspond to the densest planes of atoms in the bulk of the material. Comparing a theoretical model of i-AlPdMn with experimental results, we find that this correspondence breaks down and that surfaces parallel to the densest planes in the bulk are not the most stable, i.e. they are not so-called bulk terminations. The correspondence can be restored by recognizing that there is a contribution to the surface not just from one geometrical plane but from a layer of stacked atoms, possibly containing more than one plane. We find that not only does the stability of high-symmetry surfaces match the density of the corresponding layer-like bulk terminations but the exact spacings between surface terraces and their degree of pittedness may be determined by a simple analysis of the density of layers predicted by the bulk geometric model.Comment: 8 pages of ps-file, 3 Figs (jpg

Quantum Circuits for Measuring Levin-Wen Operators

We construct quantum circuits for measuring the commuting set of vertex and plaquette operators that appear in the Levin-Wen model for doubled Fibonacci anyons. Such measurements can be viewed as syndrome measurements for the quantum error-correcting code defined by the ground states of this model (the Fibonacci code). We quantify the complexity of these circuits with gate counts using different universal gate sets and find these measurements become significantly easier to perform if n-qubit Toffoli gates with n = 3,4 and 5 can be carried out directly. In addition to measurement circuits, we construct simplified quantum circuits requiring only a few qubits that can be used to verify that certain self-consistency conditions, including the pentagon equation, are satisfied by the Fibonacci code.Comment: 12 pages, 13 figures; published versio

The twisted gradient flow coupling at one loop

We compute the one-loop running of the $SU(N)$ 't Hooft coupling in a finite volume gradient flow scheme using twisted boundary conditions. The coupling is defined in terms of the energy density of the gradient flow fields at a scale $\tilde{l}$ given by an adequate combination of the torus size and the rank of the gauge group, and is computed in the continuum using dimensional regularization. We present the strategy to regulate the divergences for a generic twist tensor, and determine the matching to the $\overline{\rm MS}$ scheme at one-loop order. For the particular case in which the twist tensor is non-trivial in a single plane, we evaluate the matching coefficient numerically and determine the ratio of $\Lambda$ parameters between the two schemes. We analyze the $N$ dependence of the results and the possible implications for non-commutative gauge theories and volume independence.Comment: 52 pages, 12 figure

On the group of a rational maximal bifix code

We give necessary and sufficient conditions for the group of a rational maximal bifix code $Z$ to be isomorphic with the $F$-group of $Z\cap F$, when $F$ is recurrent and $Z\cap F$ is rational. The case where $F$ is uniformly recurrent, which is known to imply the finiteness of $Z\cap F$, receives special attention. The proofs are done by exploring the connections with the structure of the free profinite monoid over the alphabet of $F$

A technique for evaluating the application of the pin-level stuck-at fault model to VLSI circuits

Accurate fault models are required to conduct the experiments defined in validation methodologies for highly reliable fault-tolerant computers (e.g., computers with a probability of failure of 10 to the -9 for a 10-hour mission). Described is a technique by which a researcher can evaluate the capability of the pin-level stuck-at fault model to simulate true error behavior symptoms in very large scale integrated (VLSI) digital circuits. The technique is based on a statistical comparison of the error behavior resulting from faults applied at the pin-level of and internal to a VLSI circuit. As an example of an application of the technique, the error behavior of a microprocessor simulation subjected to internal stuck-at faults is compared with the error behavior which results from pin-level stuck-at faults. The error behavior is characterized by the time between errors and the duration of errors. Based on this example data, the pin-level stuck-at fault model is found to deliver less than ideal performance. However, with respect to the class of faults which cause a system crash, the pin-level, stuck-at fault model is found to provide a good modeling capability