Graphical modelling of modular machines

This research is aimed at advancing machine design through specifying and implementing (in "proof of concept" form) a set of tools which graphically model modular machines. The tools allow mechanical building elements (or machine modules) to be selected and configured together in a highly flexible manner so that operation of the chosen configuration can be simulated and performance properties evaluated. Implementation of the tools has involved an extension in capability of a proprietary robot simulation system. This research has resulted in a general approach to graphically modelling manufacturing machines built from modular elements. A focus of study has been on a decomposition of machine functionality leading to the establishment of a library of modular machine primitives. This provides a useful source of commonly required machine building elements for use by machine designers. Study has also focussed on the generation of machine configuration tools which facilitate the construction of a simulation model and ultimately the physical machine itself. Simulation aspects of machine control are also considered which depict methods of manipulating a machine model in the simulation phase. In addition methods of achieving machine programming have been considered which specify the machine and its operational tasks. Means of adopting common information data structures are also considered which can facilitate interfacing with other systems, including the physical machine system constructed as an issue of the simulation phase. Each of these study areas is addressed in its own context, but collectively they provide a means of creating a complete modular machine design environment which can provide significant assistance to machine designers. Part of the methodology employed in the study is based on the use of the discrete event simulation technique. To easily and effectively describe a modular machine and its activity in a simulation model, a hierarchical ring and tree data structure has been designed and implemented. The modularity and reconfigurability are accommodated by the data structure, and homogeneous transformations are adopted to determine the spatial location and orientation of each of the machine elements. A three-level machine task programming approach is used to describe the machine's activities. A common data format method is used to interface the machine design environment with the physical machine and other building blocks of manufacturing systems (such as CAD systems) where systems integration approaches can lead to enhanced product realisation. The study concludes that a modular machine design environment can be created by employing the graphical simulation approach together with a set of comprehensive configuration. tools. A generic framework has been derived which outlines the way in which machine design environments can be constructed and suggestions are made as to how the proof of concept design environment implemented in this study can be advanced

Motion control and synchronisation of multi-axis drive systems

Motion control and synchronisation of multi-axis drive system

A new approach to the development and maintenance of industrial sequence logic

This thesis is concerned with sequence logic as found in industrial control systems, with the focus being on process and manufacturing control systems. At its core is the assertion that there is a need for a better approach to the development of industrial sequence logic to satisfy the life-cycle requirements, and that many of the ingredients required to deliver such an approach are now available. The needs are discussed by considering the business case for automation and deficiencies with traditional approaches. A set of requirements is then derived for an integrated development environment to address the business needs throughout the control system life-cycle. The strengths and weaknesses of relevant control system technology and standards are reviewed and their bias towards implementation described. Mathematical models, graphical methods and software tools are then assessed with respect to the requirements for an integrated development environment. A solution to the requirements, called Synect is then introduced. Synect combines a methodology using familiar graphical notations with Petri net modelling supported by a set of software tools. Its key features are justified with reference to the requirements. A set of case studies forms the basis of an evaluation against business needs by comparing the Synect methodology with current approaches. The industrial relevance and exploitation are then briefly described. The thesis ends with a review of the key conclusions along with contributions to knowledge and suggestions for further research

Configurable 3D-integrated focal-plane sensor-processor array architecture

A mixed-signal Cellular Visual Microprocessor architecture with digital processors is described. An ASIC implementation is also demonstrated. The architecture is composed of a regular sensor readout circuit array, prepared for 3D face-to-face type integration, and one or several cascaded array of mainly identical (SIMD) processing elements. The individual array elements derived from the same general HDL description and could be of different in size, aspect ratio, and computing resources

Bilevel shared control for teleoperators

A shared system is disclosed for robot control including integration of the human and autonomous input modalities for an improved control. Autonomously planned motion trajectories are modified by a teleoperator to track unmodelled target motions, while nominal teleoperator motions are modified through compliance to accommodate geometric errors autonomously in the latter. A hierarchical shared system intelligently shares control over a remote robot between the autonomous and teleoperative portions of an overall control system. Architecture is hierarchical, and consists of two levels. The top level represents the task level, while the bottom, the execution level. In space applications, the performance of pure teleoperation systems depend significantly on the communication time delays between the local and the remote sites. Selection/mixing matrices are provided with entries which reflect how each input's signals modality is weighted. The shared control minimizes the detrimental effects caused by these time delays between earth and space

Design Time Methodology for the Formal Modeling and Verification of Smart Environments

Smart Environments (SmE) are intelligent and complex due to smart connectivity and interaction of heterogeneous devices achieved by complicated and sophisticated computing algorithms. Based on their domotic and industrial applications, SmE system may be critical in terms of correctness, reliability, safety, security and other such vital factors. To achieve error-free and requirement-compliant implementation of these systems, it is advisable to enforce a design process that may guarantee these factors by adopting formal models and formal verification techniques at design time. The e-Lite research group at Politecnico di Torino is developing solutions for SmE based on integration of commercially available home automation technologies with an intelligent ecosystem based on a central OSGi-based gateway, and distributed collaboration of intelligent applications, with the help of semantic web technologies and applications. The main goal of my research is to study new methodologies which are used for the modeling and verification of SmE. This goal includes the development of a formal methodology which ensures the reliable implementation of the requirements on SmE, by modeling and verifying each component (users, devices, control algorithms and environment/context) and the interaction among them, especially at various stages in design time, so that all the complexities and ambiguities can be reduced

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

We discuss VThreads, a novel VLIW CMP with hardware-assisted shared-memory Thread support. VThreads supports Instruction Level Parallelism via static multiple-issue and Thread Level Parallelism via hardware-assisted POSIX Threads along with extensive customization. It allows the instantiation of tightlycoupled streaming accelerators and supports up to 7-address Multiple-Input, Multiple-Output instruction extensions. VThreads is designed in technology-independent Register-Transfer-Level VHDL and prototyped on 40 nm and 28 nm Field-Programmable gate arrays. It was evaluated against a PThreads-based multiprocessor based on the Sparc-V8 ISA. On a 65 nm ASIC implementation VThreads achieves up to x7.2 performance increase on synthetic benchmarks, x5 on a parallel Mandelbrot implementation, 66% better on a threaded JPEG implementation, 79% better on an edge-detection benchmark and ~13% improvement on DES compared to the Leon3MP CMP. In the range of 2 to 8 cores VThreads demonstrates a post-route (statistical) power reduction between 65% to 57% at an area increase of 1.2%-10% for 1-8 cores, compared to a similarly-configured Leon3MP CMP. This combination of micro-architectural features, scalability, extensibility, hardware support for low-latency PThreads, power efficiency and area make the processor an attractive proposition for low-power, deeply-embedded applications requiring minimum OS support

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

DoMAIns: Domain-based Modeling for Ambient Intelligence

Ambient Intelligence and Smart Home Automation systems are currently emerging as feasible and ready to exploit solutions to support more intelligent features inside future and current homes. Thanks to increased availability of off-the-shelf components and to relatively easy to implement solutions we are experiencing a steady evolution of households, causing an ever-increasing users’ awareness of the capabilities of such innovative environments. To foster effective adoption of Smart Home Automation technologies in our home environments, traditional architectural and plant design must be complemented by sound design methodologies and tools, supporting the whole environment design cycle, including for example modeling, simulation and emulation, as well as, when feasible, formal model-checking and verification. Several research efforts have already addressed the design of expressive modeling tools, mostly based on Semantic Web technologies, as well as of suitable platforms for adding interoperation and rule-based intelligence to home environments. This paper proposes a new modeling methodology designed to fit the different phases of Intelligent Environments design, with a particular focus on validation and verification of the whole system. Carefully designed separation of modeled entities permits to exploit the DoMAIns framework during all phases of the environment design, from early abstract conception to the final in-field deployment. The DoMAIns design methodology is applied to a sample use case that involves comprehensive modeling and simulation of a Bank Security Booth, including the environment, the control algorithms, the automation devices and the user. Results show that the approach is feasible and that can easily handle different types of environment modeling, required in the different design phases, and for each of them it may support simulation, emulation, or other verification techniques