260 research outputs found
Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults
In the relatively young field of fault-tolerant cryptography, the main research effort has focused exclusively on the protection of the data path of cryptographic circuits. To date, however, we have not found any work that aims at protecting the control logic of these circuits against fault attacks, which thus remains the proverbial Achilles’ heel. Motivated by a hypothetical yet realistic fault analysis attack that, in principle, could be mounted against any modular exponentiation engine, even one with appropriate data path protection, we set out to close this remaining gap. In this paper, we present guidelines for the design of multifault-resilient sequential control logic based on standard Error-Detecting Codes (EDCs) with large minimum distance. We introduce a metric that measures the effectiveness of the error detection technique in terms of the effort the attacker has to make in relation to the area overhead spent in
implementing the EDC. Our comparison shows that the proposed EDC-based technique provides superior performance when compared against regular N-modular redundancy techniques. Furthermore, our technique scales well and does not affect the critical path delay
Synthesis and simulation of reprogrammable control units from hierarchical specifications
Doutoramento em Engenharia ElectrotécnicaAs máquinas finitas de estados (FSM) têm sido usadas para especificar e
implementar unidades de controlo e têm sido um assunto de grande importância
nas últimas cinco décadas. Devido ao aumento da complexidade das unidades de
controlo e uma vez que o modelo FSM não permite descrições hierárquicas e
concorrentes, novos modelos formais que suportam hierarquia e concorrência têm
sido propostos com o objectivo de ultrapassar as limitações do modelo FSM e que
permitem a especificação de unidades de controlo complexas usando uma
metodologia de decomposição hierarquizada. Apesar disso não têm sido propostas
arquitecturas de máquinas finitas de estados hierárquicas, com excepção das
máquinas construídas com memória stack, que possam ser vistas como uma
máquina integral que implementa internamente e de forma eficiente a transição
entre os diferentes níveis hierárquicos da máquina.
Esta tese aborda a síntese de máquinas de estados especificadas hierarquicamente
e propõe duas arquitecturas de máquinas hierárquicas (HFSM) e uma máquina
paralela hierárquica (PHFSM) contruídas com memória stack, que são flexíveis,
extensíveis e reutilizáveis. Apresenta também, a metodologia de síntese lógica que
permite construir a tabela de transição de estados a partir da especificação
hierárquica, tabela essa que é utilizada na implementação dos modelos propostos.
Considerando que é altamente recomendável a utilização de modelos formais que
permitam descrições hierárquicas e concorrentes na especificação de unidades de
controlo complexas, os modelos de grafos hierárquicos (HGS) e grafos paralelos
hierárquicos (PHGS) são apresentados e são feitas algumas considerações acerca
da sua utilização, execução e correcção. É ainda explicado como se pode validar a
especificação hierárquica da funcionalidade de unidades de controlo complexas
através da verificação automática e simulação da especificação baseada em HGSs.
Os modelos propostos de máquinas de estados são apresentados detalhadamente
tendo em atenção o seu funcionamento, implementação interna baseada em
memórias e sincronização, bem como as novas facilidades de flexibilidade e
extensibilidade que estes modelos apresentam.
É apresentada a metodologia manual da síntese lógica que é necessário
implementar a partir das especificações hierárquicas baseadas em HGSs ou
PHGSs de forma a construir a tabela de transição de estados que especifica a
máquina hierárquica ou paralela hierárquica, para as máquinas de estados de
Moore, Mealy ou mista Moore/Mealy. É também apresentado um programa que
implementa automaticamente a síntese lógica dos dois modelos de máquinas de
estados hierárquicas propostos a partir da especificação feita com HGSs.
Os modelos de arquitecturas propostas, bem como a metodologia de síntese,
foram validadas através de uma simulação em VHDL que foi feita usando as
ferramentas de simulação da Synopsys.Finite state machines (FSM) have been a topic of great importance in the last five
decades and have been used to specify and implement control units. Due to the
increasing complexity of control units and since the FSM model does not
explicitly support hierarchy and concurrency, new state-based models with
hierarchical and concurrent constructions were proposed in order to overcome
the limitations of the conventional FSM model and allowing the specification of
complex control units in a top-down manner. Still, there are not many hierarchical
FSM architectures (HFSM) that have been proposed to implement those
hierarchical specifications and most of them cannot be seen as a whole FSM
implementing internally in an efficient way the switching between the different
hierarchical levels of the machine, except for the HFSM with stack memory.
This thesis tackles the synthesis of FSMs from hierarchical specifications and
proposes two HFSMs and a parallel hierarchical FSM (PHFSM) with stack
memory that can provide such facilities as flexibility, extensibility and reusability.
It also presents the synthesis methodology from hierarchical specifications to the
generation of state transition tables that can be used to carry out the logic
synthesis of the proposed HFSM models.
Considering that the use of formal state-based models that provide hierarchical
and concurrent constructions is highly recommended for specifying complex
control units, hierarchical graph-schemes (HGS) and parallel hierarchical graphschemes
(PHGS) are used and some considerations about their execution and
correctness are presented. It is also explained how HGSs can be used to specify a
control algorithm and how it is possible to verify automatically its correctness and
to validate the intended functionality through simulation.
Using the first model of a HFSM with stack memory as a starting model, two new
models that can provide flexibility, extensibility and reusability and a PHFSM
model that combines hierarchy and pseudo-parallel execution of operations are
proposed. Their functionality, flexibility, extensibility, synchronisation and internal
realisation are fully explained.
To implement a control unit specified with a set of HGSs/PHGSs it is necessary
to perform the first step of the sequential logic synthesis, taking in consideration
the pretended target model. The manual synthesis methodology required to build
the state transition table of a HFSM/PHFSM starting from a hierarchical
specification based on HGSs/PHGSs is explained for a Moore, a Mealy and a
mixed Moore/Mealy FSM. A tool that automatically performs this first step for
the two HFSM models proposed is also presented.
In order to validate the proposed HFSM/PHFSM models and their synthesis, the
models were described in VHDL for a LUT-based implementation and simulated
using the Synopsys simulation tools
Introduction to Logic Circuits & Logic Design with Verilog
The overall goal of this book is to fill a void that has appeared in the instruction of digital circuits over
the past decade due to the rapid abstraction of system design. Up until the mid-1980s, digital circuits
were designed using classical techniques. Classical techniques relied heavily on manual design
practices for the synthesis, minimization, and interfacing of digital systems. Corresponding to this design
style, academic textbooks were developed that taught classical digital design techniques. Around 1990,
large-scale digital systems began being designed using hardware description languages (HDL) and
automated synthesis tools. Broad-scale adoption of this modern design approach spread through the
industry during this decade. Around 2000, hardware description languages and the modern digital
design approach began to be taught in universities, mainly at the senior and graduate level. There
were a variety of reasons that the modern digital design approach did not penetrate the lower levels of
academia during this time. First, the design and simulation tools were difficult to use and overwhelmed
freshman and sophomore students. Second, the ability to implement the designs in a laboratory setting
was infeasible. The modern design tools at the time were targeted at custom integrated circuits, which
are cost- and time-prohibitive to implement in a university setting. Between 2000 and 2005, rapid
advances in programmable logic and design tools allowed the modern digital design approach to be
implemented in a university setting, even in lower-level courses. This allowed students to learn the
modern design approach based on HDLs and prototype their designs in real hardware, mainly fieldprogrammable gate arrays (FPGAs). This spurred an abundance of textbooks to be authored, teaching
hardware description languages and higher levels of design abstraction. This trend has continued until
today. While abstraction is a critical tool for engineering design, the rapid movement toward teaching only
the modern digital design techniques has left a void for freshman- and sophomore-level courses in digital
circuitry. Legacy textbooks that teach the classical design approach are outdated and do not contain
sufficient coverage of HDLs to prepare the students for follow-on classes. Newer textbooks that teach
the modern digital design approach move immediately into high-level behavioral modeling with minimal
or no coverage of the underlying hardware used to implement the systems. As a result, students are not
being provided the resources to understand the fundamental hardware theory that lies beneath the
modern abstraction such as interfacing, gate-level implementation, and technology optimization.
Students moving too rapidly into high levels of abstraction have little understanding of what is going
on when they click the “compile and synthesize” button of their design tool. This leads to graduates who
can model a breadth of different systems in an HDL but have no depth into how the system is
implemented in hardware. This becomes problematic when an issue arises in a real design and there
is no foundational knowledge for the students to fall back on in order to debug the problem
Introduction to Logic Circuits & Logic Design with VHDL
The overall goal of this book is to fill a void that has appeared in the instruction of digital circuits over
the past decade due to the rapid abstraction of system design. Up until the mid-1980s, digital circuits
were designed using classical techniques. Classical techniques relied heavily on manual design
practices for the synthesis, minimization, and interfacing of digital systems. Corresponding to this design
style, academic textbooks were developed that taught classical digital design techniques. Around 1990,
large-scale digital systems began being designed using hardware description languages (HDL) and
automated synthesis tools. Broad-scale adoption of this modern design approach spread through the
industry during this decade. Around 2000, hardware description languages and the modern digital
design approach began to be taught in universities, mainly at the senior and graduate level. There
were a variety of reasons that the modern digital design approach did not penetrate the lower levels of
academia during this time. First, the design and simulation tools were difficult to use and overwhelmed
freshman and sophomore students. Second, the ability to implement the designs in a laboratory setting
was infeasible. The modern design tools at the time were targeted at custom integrated circuits, which
are cost- and time-prohibitive to implement in a university setting. Between 2000 and 2005, rapid
advances in programmable logic and design tools allowed the modern digital design approach to be
implemented in a university setting, even in lower-level courses. This allowed students to learn the
modern design approach based on HDLs and prototype their designs in real hardware, mainly field
programmable gate arrays (FPGAs). This spurred an abundance of textbooks to be authored teaching
hardware description languages and higher levels of design abstraction. This trend has continued until
today. While abstraction is a critical tool for engineering design, the rapid movement toward teaching only
the modern digital design techniques has left a void for freshman- and sophomore-level courses in digital
circuitry. Legacy textbooks that teach the classical design approach are outdated and do not contain
sufficient coverage of HDLs to prepare the students for follow-on classes. Newer textbooks that teach
the modern digital design approach move immediately into high-level behavioral modeling with minimal
or no coverage of the underlying hardware used to implement the systems. As a result, students are not
being provided the resources to understand the fundamental hardware theory that lies beneath the
modern abstraction such as interfacing, gate-level implementation, and technology optimization.
Students moving too rapidly into high levels of abstraction have little understanding of what is going
on when they click the “compile and synthesize” button of their design tool. This leads to graduates who
can model a breadth of different systems in an HDL but have no depth into how the system is
implemented in hardware. This becomes problematic when an issue arises in a real design and there
is no foundational knowledge for the students to fall back on in order to debug the problem
Quick Start Guide to Verilog
The classical digital design approach (i.e., manual synthesis and minimization of logic) quickly
becomes impractical as systems become more complex. This is the motivation for the modern digital
design flow, which uses hardware description languages (HDL) and computer-aided synthesis/minimization to create the final circuitry. The purpose of this book is to provide a quick start guide to the Verilog
language, which is one of the two most common languages used to describe logic in the modern digital
design flow. This book is intended for anyone that has already learned the classical digital design
approach and is ready to begin learning HDL-based design. This book is also suitable for practicing
engineers that already know Verilog and need quick reference for syntax and examples of common
circuits. This book assumes that the reader already understands digital logic (i.e., binary numbers,
combinational and sequential logic design, finite state machines, memory, and binary arithmetic basics).
Since this book is designed to accommodate a designer that is new to Verilog, the language is
presented in a manner that builds foundational knowledge first before moving into more complex topics.
As such, Chaps. 1–6 provide a comprehensive explanation of the basic functionality in Verilog to model
combinational and sequential logic. Chapters 7–11 focus on examples of common digital systems such
as finite state machines, memory, arithmetic, and computers. For a reader that is using the book as a
reference guide, it may be more practical to pull examples from Chaps. 7–11 as they use the full
functionality of the language as it is assumed the reader has gained an understanding of it in
Chaps. 1–6. For a Verilog novice, understanding the history and fundamentals of the language will
help form a comprehensive understanding of the language; thus it is recommended that the early
chapters are covered in the sequence they are written
Quick Start Guide to VHDL
The purpose of a hardware description languages is to describe digital circuitry using a text-based language. HDLs provide a means to describe large digital systems without the need for schematics, which can become impractical in very large designs. HDLs have evolved to support logic simulation at different levels of abstraction
- …