Open FPGA-based development platform for fuzzy systems with applications to communications

Soft computing techniques are gaining momentum as tools for network traffic modeling, analysis and control. Efficient hardware implementations of these techniques that can achieve real-time operation in high-speed communications equipment is however an open problem. This paper describes a platform for the development of fuzzy systems with applications to communications systems, namely network traffic analysis and control. An FPGA development board with PCI interface is employed to support an open platform that comprises open CAD tools as well as IP cores. For the development process, we set up a methodology and a CAD tools chain that cover from initial specification in a high-level language to implementation on FPGA devices. PCI compatible fuzzy inference modules are implemented as SoPC based on the open WISHBONE interconnection architecture. We outline results from the design and implementation of fuzzy analyzers and regulators for network traffic. These systems are shown to satisfy operational and architectural requirements of current and future high-performance routing equipment.Ministerio de Educación y Ciencia TEC2005-04359/MICJunta de Andalucía TIC2006-63

Modeling, Design And Evaluation Of Networking Systems And Protocols Through Simulation

Computer modeling and simulation is a practical way to design and test a system without actually having to build it. Simulation has many benefits which apply to many different domains: it reduces costs creating different prototypes for mechanical engineers, increases the safety of chemical engineers exposed to dangerous chemicals, speeds up the time to model physical reactions, and trains soldiers to prepare for battle. The motivation behind this work is to build a common software framework that can be used to create new networking simulators on top of an HLA-based federation for distributed simulation. The goals are to model and simulate networking architectures and protocols by developing a common underlying simulation infrastructure and to reduce the time a developer has to learn the semantics of message passing and time management to free more time for experimentation and data collection and reporting. This is accomplished by evolving the simulation engine through three different applications that model three different types of network protocols. Computer networking is a good candidate for simulation because of the Internet\u27s rapid growth that has spawned off the need for new protocols and algorithms and the desire for a common infrastructure to model these protocols and algorithms. One simulation, the 3DInterconnect simulator, simulates data transmitting through a hardware k-array n-cube network interconnect. Performance results show that k-array n-cube topologies can sustain higher traffic load than the currently used interconnects. The second simulator, Cluster Leader Logic Algorithm Simulator, simulates an ad-hoc wireless routing protocol that uses a data distribution methodology based on the GPS-QHRA routing protocol. CLL algorithm can realize a maximum of 45% power savings and maximum 25% reduced queuing delay compared to GPS-QHRA. The third simulator simulates a grid resource discovery protocol for helping Virtual Organizations to find resource on a grid network to compute or store data on. Results show that worst-case 99.43% of the discovery messages are able to find a resource provider to use for computation. The simulation engine was then built to perform basic HLA operations. Results show successful HLA functions including creating, joining, and resigning from a federation, time management, and event publication and subscription

Power Management Strategies for Wired Communication Networks.

With the exponential traffic growth and the rapid expansion of communication infrastructures worldwide, energy expenditure of the Internet has become a major concern in IT-reliant society. This energy problem has motivated the urgent demands of new strategies to reduce the consumption of telecommunication networks, with a particular focus on IP networks. In addition to the development of a new generation of energy-efficient network equipment, a significant body of research has concentrated on incorporating power/energy-awareness into network control and management, which aims at reducing the network power/energy consumption by either dynamically scaling speeds of each active network component to make it capable of adapting to its current load or putting to sleep the lightly loaded network elements and reconfiguring the network. However, the fundamental challenge of greening the Internet is to achieve a balance between the power/energy saving and the demands of quality-of-service (QoS) performance, which is an issue that has received less attention but is becoming a major problem in future green network designs. In this dissertation, we study how energy consumption can be reduced through different power/energy- and QoS-aware strategies for wired communication networks. To sufficiently reduce energy consumption while meeting the desire QoS requirements, we introduce several different schemes combing power management techniques with different scheduling strategies, which can be classified into experimental power management (EPM) and algorithmic power management (APM). In these proposed schemes, the power management techniques that we focus on are speed scaling and sleep mode. When the network processor is active, its speed and supply voltage can be decreased to reduce the energy consumption (speed scaling), while when the processor is idle, it can be put in a low power mode to save the energy consumption (sleep mode). The resulting problem is to determine how and when to adjust speeds for the processors, and/or to put a device into sleep mode. In this dissertation, we first discuss three families of dynamic voltage/frequency scaling (DVFS) based, QoS-aware EPM schemes, which aim to reduce the energy consumption in network equipment by using different packet scheduling strategies, while adhering to QoS requirements of supported applications. Then, we explore the problem of energy minimization under QoS constraints through a mathematical programming model, which is a DVFS-based, delay-aware APM scheme combing the speed scaling technique with the existing rate monotonic scheduling policy. Among these speed scaling based schemes, up to 26.76% dynamic power saving of the total power consumption can be achieved. In addition to speed scaling approaches, we further propose a sleep-based, traffic-aware EPM scheme, which is used to reduce power consumption by greening routing light load and putting the related network equipment into sleep mode according to twelve flow traffic density changes in 24-hour of an arbitrarily selected day. Meanwhile, a speed scaling technique without violating network QoS performance is also considered in this scheme when the traffic is rerouted. Applying this sleep-based strategy can lead to power savings of up to 62.58% of the total power consumption

A cyber-enabled mission-critical system for post-flood response:Exploiting TV white space as network backhaul links

A crucial problem in post-flood recovery actions is the ability to rapidly establish communication and collaboration among rescuers to conduct timely and effective search and rescue (SAR) mission given disrupted telecommunication infrastructure to support the service. Aimed at providing such proximity service (ProSe) for mission-critical data exchange in the post-flood environment, the majority of existing solutions rely heavily upon ad-hoc networking approaches, which suffer from restricted communication range and the limited scope of interaction. As an effort to broaden the ProSe coverage and expand integrated global-local information exchange in the post-flood SAR activities, this paper proposes a novel network architecture in the form of a cyber-enabled mission-critical system (CEMCS) for acquiring and communicating post-flood emergency data by exploiting TV white space spectrum as network backhaul links. The primary method of developing the proposed system builds upon a layered architecture of wireless local, regional and wide-area communications, and incorporates collaborative network components among these layers. The desirable functionalities of CEMCS are showcased through formulation and the development of an efficient global search strategy exploiting a wide range of collaboration among network agents. The simulation results demonstrate the capability of CEMCS to provide ProSe in the post-flood scenarios as reflected by reliable network performance (e.g., packet delivery ratio nearing 80%-90%) and the optimality of efficient search algorithm

Heterogeneous networks using mobile-IP technology

Whenever a mobile user moves between networks a handover must occur. This basically means that a network-layer protocol must handle the moving of the mobile device. In a cellular phone a GSM/UMTS infrastructure performs horizontal handover and the user does not notices any call or ongoing session interruption while roaming. The handover procedure begins when the received signal strength identificator (RSSI) of a mobile device falls below a level, it discovers a neighbour access point with better quality of services (QoS) than its current access point. In heterogeneous wireless networks different portions of RF spectrum are used and is difficult or impossible for a mobile node to concurrently maintain its connectivity without signal interruptions. Thus, the different network environments must be integrated and support a common platform to achieve seamless handover. The seamless or vertical handover's target is to maintain the mobile user's IP address independently of user's location or of the physical parameters the current network is using. A mechanism that keeps a mobile device to an ongoing connection by maintaining its home-location IP address is the Mobile-IP protocol which operates at the network-layer of the Open System Interconnection (OSI) model. In this M.Sc. thesis we perform heterogeneous network scenarios with the Mobile-IP technology. Moreover, we have built the system practically and assist the applicability of such heterogeneous wireless networks through real-side measurements. We used Linux operating system (Ubuntu & Debian) between different network technologies, made at the National Center for Scientific Research (NCSR) ''Demokritos'' institute, in Greece. The required applications for the Mobile-IP and 3G technologies were implemented and configured in a platform of fixed and mobile devices at Demokrito's departmental laboratory. The idea of using the Mobile-IP protocol was to gather information about time differences that occurred in handover delay between different networks.fi=Opinnäytetyö kokotekstinä PDF-muodossa.|en=Thesis fulltext in PDF format.|sv=Lärdomsprov tillgängligt som fulltext i PDF-format

Telephony Denial of Service Defense at Data Plane (TDoSD@DP)

The Session Initiation Protocol (SIP) is an application-layer control protocol used to establish and terminate calls that are deployed globally. A flood of SIP INVITE packets sent by an attacker causes a Telephony Denial of Service (TDoS) incident, during which legitimate users are unable to use telephony services. Legacy TDoS defense is typically implemented as network appliances and not sufficiently deployed to enable early detection. To make TDoS defense more widely deployed and yet affordable, this paper presents TDoSD@DP where TDoS detection and mitigation is programmed at the data plane so that it can be enabled on every switch port and therefore serves as distributed SIP sensors. With this approach, the damage is isolated at a particular switch and bandwidth saved by not sending attack packets further upstream. Experiments have been performed to track the SIP state machine and to limit the number of active SIP session per port. The results show that TDoSD@DP was able to detect and mitigate ongoing INVITE flood attack, protecting the SIP server, and limiting the damage to a local switch. Bringing the TDoS defense function to the data plane provides a novel data plane application that operates at the SIP protocol and a novel approach for TDoS defense implementation.Final Accepted Versio

Developoing A Computer and Network Engineering Major Curriculum For Vocational High School (VHS) in Indonesia

This study aims at developing curriculum for Computer and Network Engineering major which is relevant to industrial needs. The study employed the qualitative method. The data were collected through an in-depth interview, documentation, and focus group disscussion. The research population comprised of (1) industry practitioners from computer and network engineering industries, and (2) teachers of vocational high schools in Special Region of Yogyakarta. In this qualitative research, the one who became the instrument or tool of the research was the researcher himself. Understanding the qualitative research method and the knowledge related to the field of the research, the researcher was sure that he had sufficient knowledge both academically and technically. The findings of this study consisted of four parts, namely (1) standard competence of Computer and Network Engineering major for vocational high school; (2) the curriculum of Computer and Network Engineering major that is currently implemented; (3) competences in the field of Computer and Network Engineering demanded by industries; and (4) the curricuulum of Computer and Network Engineering major that is appropriate for industrial needs

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC\u2710 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551)

ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. The workshop aims to provide a prospective view of tomorrow\u27s challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability

Off-chip Communications Architectures For High Throughput Network Processors

In this work, we present off-chip communications architectures for line cards to increase the throughput of the currently used memory system. In recent years there is a significant increase in memory bandwidth demand on line cards as a result of higher line rates, an increase in deep packet inspection operations and an unstoppable expansion in lookup tables. As line-rate data and NPU processing power increase, memory access time becomes the main system bottleneck during data store/retrieve operations. The growing demand for memory bandwidth contrasts the notion of indirect interconnect methodologies. Moreover, solutions to the memory bandwidth bottleneck are limited by physical constraints such as area and NPU I/O pins. Therefore, indirect interconnects are replaced with direct, packet-based networks such as mesh, torus or k-ary n-cubes. We investigate multiple k-ary n-cube based interconnects and propose two variations of 2-ary 3-cube interconnect called the 3D-bus and 3D-mesh. All of the k-ary n-cube interconnects include multiple, highly efficient techniques to route, switch, and control packet flows in order to minimize congestion spots and packet loss. We explore the tradeoffs between implementation constraints and performance. We also developed an event-driven, interconnect simulation framework to evaluate the performance of packet-based off-chip k-ary n-cube interconnect architectures for line cards. The simulator uses the state-of-the-art software design techniques to provide the user with a flexible yet robust tool, that can emulate multiple interconnect architectures under non-uniform traffic patterns. Moreover, the simulator offers the user with full control over network parameters, performance enhancing features and simulation time frames that make the platform as identical as possible to the real line card physical and functional properties. By using our network simulator, we reveal the best processor-memory configuration, out of multiple configurations, that achieves optimal performance. Moreover, we explore how network enhancement techniques such as virtual channels and sub-channeling improve network latency and throughput. Our performance results show that k-ary n-cube topologies, and especially our modified version of 2-ary 3-cube interconnect - the 3D-mesh, significantly outperform existing line card interconnects and are able to sustain higher traffic loads. The flow control mechanism proved to extensively reduce hot-spots, load-balance areas of high traffic rate and achieve low transmission failure rate. Moreover, it can scale to adopt more memories and/or processors and as a result to increase the line card\u27s processing power