2,791 research outputs found
Reconfigurable interconnects in DSM systems: a focus on context switch behavior
Recent advances in the development of reconfigurable optical interconnect technologies allow for the fabrication of low cost and run-time adaptable interconnects in large distributed shared-memory (DSM) multiprocessor machines. This can allow the use of adaptable interconnection networks that alleviate the huge bottleneck present due to the gap between the processing speed and the memory access time over the network. In this paper we have studied the scheduling of tasks by the kernel of the operating system (OS) and its influence on communication between the processing nodes of the system, focusing on the traffic generated just after a context switch. We aim to use these results as a basis to propose a potential reconfiguration of the network that could provide a significant speedup
When parallel speedups hit the memory wall
After Amdahl's trailblazing work, many other authors proposed analytical
speedup models but none have considered the limiting effect of the memory wall.
These models exploited aspects such as problem-size variation, memory size,
communication overhead, and synchronization overhead, but data-access delays
are assumed to be constant. Nevertheless, such delays can vary, for example,
according to the number of cores used and the ratio between processor and
memory frequencies. Given the large number of possible configurations of
operating frequency and number of cores that current architectures can offer,
suitable speedup models to describe such variations among these configurations
are quite desirable for off-line or on-line scheduling decisions. This work
proposes new parallel speedup models that account for variations of the average
data-access delay to describe the limiting effect of the memory wall on
parallel speedups. Analytical results indicate that the proposed modeling can
capture the desired behavior while experimental hardware results validate the
former. Additionally, we show that when accounting for parameters that reflect
the intrinsic characteristics of the applications, such as degree of
parallelism and susceptibility to the memory wall, our proposal has significant
advantages over machine-learning-based modeling. Moreover, besides being
black-box modeling, our experiments show that conventional machine-learning
modeling needs about one order of magnitude more measurements to reach the same
level of accuracy achieved in our modeling.Comment: 24 page
Sphinx: A Secure Architecture Based on Binary Code Diversification and Execution Obfuscation
Sphinx, a hardware-software co-design architecture for binary code and
runtime obfuscation. The Sphinx architecture uses binary code diversification
and self-reconfigurable processing elements to maintain application
functionality while obfuscating the binary code and architecture states to
attackers. This approach dramatically reduces an attacker's ability to exploit
information gained from one deployment to attack another deployment. Our
results show that the Sphinx is able to decouple the program's execution time,
power and memory and I/O activities from its functionality. It is also
practical in the sense that the system (both software and hardware) overheads
are minimal.Comment: Boston Area Architecture 2018 Workshop (BARC18
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