Development of an Online Bus Ticket Reservation System for a Transportation Service in Nigeria

The use of bus traveling is a large growing business in Nigeria and other countries; the manual use of bus reservation is presently very strenuous and also consumes a lot of time by having to stay on a long queue. For this reason, an efficient system is to be proposed in this paper to ease the issue of bus reservation amongst indigenes within the country. The system is a web – based application that allows visitors to check bus availability, buy and pay bus ticket online. In this paper, the proposed bus reservation system was developed using Extensible Hypertext Markup Language (XHTML), PHP Hypertext Preprocessor (PHP), Structure Query Language (SQL), Ajax, Cascading Style Sheet (CSS), and JavaScript. Keywords: Bus Reservation, Queue, Efficient

Departure processes from MAP/PH/1 queues

A MAP/PH/1 queue is a queue having a Markov arrival process (MAP), and a single server with phase-type (PH -type) distributed service time. This thesis considers the departure process from these type of queues. We use matrix analytic methods, the Jordan canonical form of matrices, non-linear filtering and approximation techniques. The departure process of a queue is important in the analysis of networks of queues, as it may be the arrival process to another queue in the network. If a simple description were to exist for a departure process, the analysis of at least feed-forward networks of these queues would then be analytically tractable. Chapter 1 is an introduction to some of the literature and ideas surrounding the departure process from MAP/PH/1 queues. Chapter 2 sets up the basic notation and establishes some results which are used throughout the thesis. It contains a preliminary consideration of PH -type distributions, PH -renewal processes, MAP s, MAP/PH/1 queues, non-linear filtering and the Jordan canonical form. Chapter 3 is an expansion of "The Output process of an MMPP/M/1 queue", where the question of whether a MAP description can exist for the departure process of a non-trivial MAP/M/1 queue is considered. In a 1994 paper, Olivier and Walrand conjectured that the departure process of a MAP/PH/1 queue is not a MAP unless the queue is a stationary M/M/1 queue. This conjecture was prompted by their claim that the departure process of an MMPP/M/1 queue is not MAP unless the queue is a stationary M/M/1 queue. We show that their proof has an algebraic error, which leaves open the above question of whether the departure process of an MMPP/PH/1 queue is a MAP or not. In Chapter 4, the more fundamental problem of identifying stationary M/M/1 queues in the class of MAP/PH/1 queues is considered. It is essential to be able to determine from its generator when a stationary MAP is a Poisson process. This does not appear to have been discussed in the literature prior to the author's paper, where this deficiency was remedied using ideas from non-linear filtering theory, to give a characterisation as to when a stationary MAP is a Poisson process. Chapter 4 expands upon "When is a MAP Poisson". This investigation of higher order representations of the Poisson process is motivated by first considering when a higher order PH -type distribution is just negative exponential. In Chapter 5, we consider the related question of minimal order representations for PH -type distributions, an issue which has attracted much interest in the literature. A discussion of other authors' ideas is given and these ideas are then inter-related to the work presented in Chapter 4 on the PH -type distributions. The MAP/M/1 queue is then considered in Chapter 6 from the perspective of whether having an exact level and phase independent stationary distribution of the geometric form [Formula - Not available: see pdf version of the abstract] implies that the MAP is Poisson. The answer is in the affirmative for this question, but the converse is not strictly true. Apart from showing the ubiquitous asymptotic form of level and phase independence exhibited by all stable MAP/M/1 queues, we prove that a very large class of stable queues, exhibits what we have termed shift-one level and phase independence. Stable MAP/M/1 queues exhibiting shift-one level and phase independence, are characterised by a stationary distribution of the following form: [Formula - Not Available: see pdf version of the abstract] In Chapter 7, a family of approximations is proposed for the output process of a stationary MAP/PH/1 queue. To check the viability of these approximations, they are used as input to another single server queue. Performance measures for the second server are obtained analytically in both the tandem and approximation cases, thus eliminating the need for simulation to compare results. Comparison of these approximations is also made against other approximation methods in the literature. In Chapter 8, we show that our approximations from Chapter 7 have the property of exactly matching the inter-departure time distribution. Our kth approximation also accurately captures the first k-1 lag-correlation coefficients of the stationary departure process. The proofs of this direct association between lag-correlation coefficients and the level of complexity k are given.Thesis (Ph.D.)--School of Applied Mathematics, 1999

Low-complexity distributed issue queue

As technology evolves, power density significantly increases and cooling systems become more complex and expensive. The issue logic is one of the processor hotspots and, at the same time, its latency is crucial for the processor performance. We present a low-complexity FP issue logic (MB/spl I.bar/distr) that achieves high performance with small energy requirements. The MB/spl I.bar/distr scheme is based on classifying instructions and dispatching them into a set of queues depending on their data dependences. These instructions are selected for issuing based on an estimation of when their operands will be available, so the conventional wakeup activity is not required. Additionally, the functional units are distributed across the different queues. The energy required by the proposed scheme is substantially lower than that required by a conventional issue design, even if the latter has the ability of waking-up only unready operands. MB/spl I.bar/distr scheme reduces the energy-delay product by 35% and the energy-delay product by 18% with respect to a state-of-the-art approach.Peer ReviewedPostprint (published version

Efficient resources assignment schemes for clustered multithreaded processors

New feature sizes provide larger number of transistors per chip that architects could use in order to further exploit instruction level parallelism. However, these technologies bring also new challenges that complicate conventional monolithic processor designs. On the one hand, exploiting instruction level parallelism is leading us to diminishing returns and therefore exploiting other sources of parallelism like thread level parallelism is needed in order to keep raising performance with a reasonable hardware complexity. On the other hand, clustering architectures have been widely studied in order to reduce the inherent complexity of current monolithic processors. This paper studies the synergies and trade-offs between two concepts, clustering and simultaneous multithreading (SMT), in order to understand the reasons why conventional SMT resource assignment schemes are not so effective in clustered processors. These trade-offs are used to propose a novel resource assignment scheme that gets and average speed up of 17.6% versus Icount improving fairness in 24%.Peer ReviewedPostprint (published version

Late allocation and early release of physical registers

The register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the size and number of ports of the register file. In conventional register renaming schemes, both register allocation and releasing are conservatively done, the former at the rename stage, before registers are loaded with values, and the latter at the commit stage of the instruction redefining the same register, once registers are not used any more. We introduce VP-LAER, a renaming scheme that allocates registers later and releases them earlier than conventional schemes. Specifically, physical registers are allocated at the end of the execution stage and released as soon as the processor realizes that there will be no further use of them. VP-LAER enhances register utilization, that is, the fraction of allocated registers having a value to be read in the future. Detailed cycle-level simulations show either a significant speedup for a given register file size or a reduction in the register file size for a given performance level, especially for floating-point codes, where the register file pressure is usually high.Peer ReviewedPostprint (published version

Inherently workload-balanced clustered microarchitecture

The performance of clustered microarchitectures relies on steering schemes that try to find the best trade-off between workload balance and inter-cluster communication penalties. In previously proposed clustered processors, reducing communication penalties and balancing the workload are opposite targets, since improving one usually implies a detriment in the other. In this paper we propose a new clustered microarchitecture that can minimize communication penalties without compromising workload balance. The key idea is to arrange the clusters in a ring topology in such a way that results of one cluster can be forwarded to the neighbor cluster with a very short latency. In this way, minimizing communication penalties is favored when the producer of a value and its consumer are placed in adjacent clusters, which also favors workload balance. The proposed microarchitecture is shown to outperform a state-of-the-art clustered processor. For instance, for an 8-cluster configuration and just one fully pipelined unidirectional bus, 15% speedup is achieved on average for FP programs.Peer ReviewedPostprint (published version