Circuit Simulation Models for Coming MOSFET Generations

Abstract-The urgent tasks of MOSFET modeling for circuit simulation are easy adaptation to new physical phenomena arising for advancing technologies, and, of course, sufficient simulation accuracy. Approaches currently being pursued for developing such MOSFET models are summarized. Their capabilities for accomplishing these tasks as well as the important remaining problems are discussed

Analytical predictive 2d modeling of pinch-off behavior in nanoscale multi-gate mosfets

In this thesis the pinch-off behavior in nanoscale Multi-Gate MOSFETs was reviewed and with compact models described. For this a 2D approach with Schwarz-Christoffel conformal mapping technique was used. A model to calculate the current in single gate MOSFETs was derived and compared to device simulations from TCAD Sentaurus down to 50nm. For the DoubleGate MOSFET a new way to define the saturation point was found. A fully 2D closed-form model to locate this point was created. It was also found that with quantum mechanics effects a pinch-off point can occur and can be described with the same model. Furthermore the model was extended to describe the coupled pinch-off points in an asymmetrical biased DoubleGate MOSET with an even an odd mode. Also the saturation point behavior in FinFETs was examinated

Semiconductor Device Modeling and Simulation for Electronic Circuit Design

This chapter covers different methods of semiconductor device modeling for electronic circuit simulation. It presents a discussion on physics-based analytical modeling approach to predict device operation at specific conditions such as applied bias (e.g., voltages and currents); environment (e.g., temperature, noise); and physical characteristics (e.g., geometry, doping levels). However, formulation of device model involves trade-off between accuracy and computational speed and for most practical operation such as for SPICE-based circuit simulator, empirical modeling approach is often preferred. Thus, this chapter also covers empirical modeling approaches to predict device operation by implementing mathematically fitted equations. In addition, it includes numerical device modeling approaches, which involve numerical device simulation using different types of commercial computer-based tools. Numerical models are used as virtual environment for device optimization under different conditions and the results can be used to validate the simulation models for other operating conditions

RF Compact Modeling of High-voltage MOSFETs

The High-Voltage MOSFET is used in a wide variety of applications covering from power systems up to RF-IC. Compact models that describe the high-frequency behavior of the device are required to predict high-frequency operation and switching capabilities of these elements in HV state-of-the-art systems. In this paper, an RF model is presented and verified against extensive Y-parameter measurements, which were carried out on a long channel Lateral double-Diffusion MOS device. Assessment of the model with measurements confirms the validity of this approach

Contribution à la modélisation des dispositifs MOS haute tension pour les circuits intégrés de puissance ("Smart Power")

Au cours des dernières décennies, les circuits intégrés de puissance ont connu une croissance très importante. Aujourd'hui la régulation et distribution d'énergie électrique jouent un rôle crucial. La réduction constante des dimensions ainsi que le besoin en densité de puissance de plus en plus élevée ont mis en évidence la nécessité de structures toujours plus performantes. La technologie “smart power” a été développée pour satisfaire ces demandes. Cette technologie utilise les dispositifs DMOS, offrant de nouvelles solutions grâce à ses caractéristiques uniques forte tension et fort courant. Le fonctionnement de ces dispositifs est accompagné par l’apparition de nombreux phénomènes. Une bonne modélisation permet de rendre compte de ces phénomènes et prédire le comportement physique du transistor avant sa production. L'objectif de cette thèse était donc d'améliorer la modélisation et de mettre en place une méthode d'extraction de certains paramètres physiques liés au fonctionnement du MOS HV (High Voltage). Cette thèse a été principalement dédiée à la modélisation du phénomène de l'auto-échauffement et à la définition d'une méthode d'extraction des parasites RF dans les transistors MOS et, enfin, à la comparaison du macro-modèle utilisé par STMicroelectronics avec le modèle compact HiSIM_HV dédié au MOS HV. Pour cela, il était essentiel de mettre en place des nouvelles procédures de modélisation et d'extraction et de dessiner des structures de test spécifiques. Les résultats présentés dans cette thèse ont été validés par différentes comparaisons avec les mesures en technologies sur SOI et sur substrat massif.In recent decades, power integrated circuits have experienced very significant growth. Today the regulation and distribution of electrical energy are crucial. The reduction of the dimensions and the need for power highlighted the need for efficient structures. Technology "smart power" has been developed to meet these demands. This technology uses high voltage devices, offering new solutions through its unique characteristics at high voltages and currents. The behavior of these devices is accompanied by the appearance of many phenomena. An accurate modeling of these phenomena is needed to replicate its physical behavior. The objective of this thesis is to improve modeling and to establish a good method of extracting physical parameters related to HV MOS. This thesis has been mainly devoted to modeling the phenomenon of self-heating: development of test structure, modeling of thermal coupling between the sources of transistor, development tool for generating the thermal network. This thesis also looks at the definition of a method for extracting RF noise in the high-voltage transistor including extrinsic gate resistance and capacity Cgs and Cgd. Finally, the last part of the thesis presents a brief assessment of compact HiSIM_HV dedicated to HV MOS and compares it with the macro model used by STMicroelectronics. The results presented in this thesis have been validated by comparison with different measures on SOI technology and solid substrate

Modeling of the Electrical Characteristics of an Organic Field Effect Transistor in Presence of the Bending Effects

An analytical model incorporating the density of trap states for a bendable organic field effect transistor (OFET) is presented in this paper. The aim of this work is to propose a novel modeling framework to quantitatively characterize the bending effects on the electrical properties of an OFET in the linear and saturation regimes. In this model, the exponentially distributed shallow trap states are introduced into the Poisson equation to describe the carrier transports in the channel. The carrier mobility takes into account the low field mobility enhancement under gradual channel approximation and high field degradation. As a result, the generalized current-voltage transistor equations are derived for the first time to reflect the transconductance relationships of the OFET with trap states. In addition, an electro-mechanical coupling relationship is established per the metaphorical analogy between inorganic and organic semiconductor energy band models to quantify the stress-induced variations of the carrier mobility, and the threshold voltage. It is revealed that the before- and after-bending transconductances, predicted from the derived analytical model, are in good agreement with the experimental data measured from DNTT-based OFET bending tests