503 research outputs found

    A scheduling strategy for shared memory multiprocessors

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    technical reportAn efficient scheduling strategy for shared memory multiprocessors is described. The rapid dissemination of tasks to available procesors and ready queues is crucial to the performance of any parallel system. Such overheads determine the attainable speedup and performance of the system. Poor techniques used to address this can lead to severe degradation in performance particulary with high processor counts. This work has been conducted in the context of a parallel functional language-CoF, where the parallelism is usually fine grained and the efficient assignment of tasks to processors even more important. In such systems, observing strict queue semantics (i.e., FIFO) is not essesntial. This allows for very efficient algorithms such as that described here. On the BBN GP1000, our technique was superior in performance to the centralized queue and has the potential of performing well on a fully configured GP1000

    Energy reduction in multiprocessor systems using transactional memory

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    Simulation models of shared-memory multiprocessor systems

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    Performance Debugging and Tuning using an Instruction-Set Simulator

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    Instruction-set simulators allow programmers a detailed level of insight into, and control over, the execution of a program, including parallel programs and operating systems. In principle, instruction set simulation can model any target computer and gather any statistic. Furthermore, such simulators are usually portable, independent of compiler tools, and deterministic-allowing bugs to be recreated or measurements repeated. Though often viewed as being too slow for use as a general programming tool, in the last several years their performance has improved considerably. We describe SIMICS, an instruction set simulator of SPARC-based multiprocessors developed at SICS, in its rôle as a general programming tool. We discuss some of the benefits of using a tool such as SIMICS to support various tasks in software engineering, including debugging, testing, analysis, and performance tuning. We present in some detail two test cases, where we've used SimICS to support analysis and performance tuning of two applications, Penny and EQNTOTT. This work resulted in improved parallelism in, and understanding of, Penny, as well as a performance improvement for EQNTOTT of over a magnitude. We also present some early work on analyzing SPARC/Linux, demonstrating the ability of tools like SimICS to analyze operating systems

    The java.util.concurrent synchronizer framework

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    AbstractMost synchronizers (locks, barriers, etc.) in the J2SE 5.0 java.util.concurrent package are constructed using a small framework based on class AbstractQueuedSynchronizer. This framework provides common mechanics for atomically managing synchronization state, blocking and unblocking threads, and queuing. The paper describes the rationale, design, implementation, usage, and performance of this framework
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