High speed protocols for dual bus and dual ring network architectures

In this dissertation, two channel access mechanisms providing fair and bandwidth efficient transmission on dual bus and dual ring networks with high bandwidth-latency product are proposed. In addition, two effective priority mechanisms are introduced to meet the throughput and delay requirements of the diverse arrays of applications that future high speed networks must support. For dual bus architectures, the Buffer Insertion Bandwidth Balancing (BI_BWB) mechanism and the Preemptive priority Bandwidth Balancing (P_BI_BWB) mechanism are proposed. BI_BWB can significantly improve the delay performance of remote stations. It achieves that by providing each station with a shift register into which the station can temporarily store the upstream stations\u27 transmitted packets and replace these packets with its own transmissions. P_BI_BWB, an enhancement of BI_BWB, is designed to introduce effective preemptive priorities. This mechanism eliminates the effect of low priority on high priority by buffering the low priority traffic into a shift register until the transmission of the high priority traffic is complete. For dual ring architectures, the Fair Bandwidth Allocation Mechanism (FBAM) and the Effective Priority Bandwidth Balancing (EP_BWB) mechanism are introduced. FBAM allows stations to reserve channel bandwidth on a continuous basis rather than wait until bandwidth starvation is observed. Consequently, FBAM does not have to deal with the difficult issue of identifying starvation, a serious drawback of other access mechanisms such as the Local and Global Fairness Algorithms (LFA and GFA, respectively). In addition, its operation requires a significantly smaller number of control bits in the access control field of the slot and its performance is less sensitive to system parameters. Moreover, FBAM demonstrates Max-Min flow control properties with respect to the allocation of bandwidth among competing traffic streams, which is a significant advantage of FBAM over all the previously proposed channel access mechanisms. EP_BWB, an enhancement of FBAM to support preemptive priorities, minimizes the effect of low priority on high priority and supports delay-sensitive traffic by enabling higher priority classes to preempt the transmissions of lower priority classes. Finally, the great potential of EP_BWB to support the interconnection of base stations on a distributed control wireless PCN carrying voice and data traffic is demonstrated

Fair and efficient transmission over GBPS dual ring networks

The advances in fiber optics technology provide large bandwidth and enable the support of a wide variety of services. New network architectures have been proposed, such as Metaring and Distributed Queue Dual Bus (DQDB), that try to take advantage of the new capabilities. Because of the very small packet transmission time relative to the feedback time a challenging issue in high speed networks is the efficient and fair share of the channel bandwidth among the competing users. In this thesis we first investigate and compare the performance of the Global and Local Fairness Mechanisms (GFM and LFM, respectively). They have been proposed recently for fair bandwidth allocation in high speed dual ring networks employing destination release. (a slot that has been read by its destination is immediately released and can be used again by other nodes). We show the sensitivity of both mechanisms to various system parameters, such as channel bandwidth and ring latency. We introduce the Dynamic Medium Access Control Mechanism (DMAC) which does not suffer from the limitations of GFM and LFM, introduces fairness in a very effective and efficient way, and is insensitive to the network parameters

Medium access control mechanisms for high speed metropolitan area networks

In this dissertation novel Medium Access Control mechanisms for High Speed Metropolitan Area networks are proposed and their performance is investigated under the presence of single and multiple priority classes of traffic. The proposed mechanisms are based on the Distributed Queue Dual Bus network, which has been adopted by the IEEE standardization committee as the 802.6 standard for Metropolitan Area Networks, and address most of its performance limitations. First, the Rotating Slot Generator scheme is introduced which uses the looped bus architecture that has been proposed for the 802.6 network. According to this scheme the responsibility for generating slots moves periodically from station to station around the loop. In this way, the positions of the stations relative to the slot generator change continuously, and therefore, there are no favorable locations on the busses. Then, two variations of a new bandwidth balancing mechanism, the NSW_BWB and ITU_NSW are introduced. Their main advantage is that their operation does not require the wastage of channel slots and for this reason they can converge very fast to the steady state, where the fair bandwidth allocation is achieved. Their performance and their ability to support multiple priority classes of traffic are thoroughly investigated. Analytic estimates for the stations\u27 throughputs and average segment delays are provided. Moreover, a novel, very effective priority mechanism is introduced which can guarantee almost immediate access for high priority traffic, regardless of the presence of lower priority traffic. Its performance is thoroughly investigated and its ability to support real time traffic, such as voice and video, is demonstrated. Finally, the performance under the presence of erasure nodes of the various mechanisms that have been proposed in this dissertation is examined and compared to the corresponding performance of the most prominent existing mechanisms

MAC Aspects of Millimeter-Wave Cellular Networks

The current demands for extremely high data rate wireless services and the spectrum scarcity at the sub-6 GHz bands are forcefully motivating the use of the millimeter-wave (mmWave) frequencies. MmWave communications are characterized by severe attenuation, sparse-scattering environment, large bandwidth, high penetration loss, beamforming with massive antenna arrays, and possible noise-limited operation. These characteristics imply a major difference with respect to legacy communication technologies, primarily designed for the sub-6 GHz bands, and are posing major design challenges on medium access control (MAC) layer. This book chapter discusses key MAC layer issues at the initial access and mobility management (e.g., synchronization, random access, and handover) as well as resource allocation (interference management, scheduling, and association). The chapter provides an integrated view on MAC layer issues for cellular networks and reviews the main challenges and trade-offs and the state-of-the-art proposals to address them

Full utilization, fairness and bounded access delay on high speed bus networks

Caption title.Includes bibliographical references (p. 31-32).Supported by ARPA. MDA972-92-J-1038Angela L. Chiu, Robert G. Gallager

Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms

Multiprocessor Systems-on-Chip (MPSoC) integrating hard processing cores with programmable logic (PL) are becoming increasingly common. While these platforms have been originally designed for high performance computing applications, their rich feature set can be exploited to efficiently implement mixed criticality domains serving both critical hard real-time tasks, as well as soft real-time tasks. In this paper, we take a deep look at commercially available heterogeneous MPSoCs that incorporate PL and a multicore processor. We show how one can tailor these processors to support a mixed criticality system, where cores are strictly isolated to avoid contention on shared resources such as Last-Level Cache (LLC) and main memory. In order to avoid conflicts in last-level cache, we propose the use of cache coloring, implemented in the Jailhouse hypervisor. In addition, we employ ScratchPad Memory (SPM) inside the PL to support a multi-phase execution model for real-time tasks that avoids conflicts in shared memory. We provide a full-stack, working implementation on a latest-generation MPSoC platform, and show results based on both a set of data intensive tasks, as well as a case study based on an image processing benchmark application

A Bandwidth Control Arbitration for SoC Interconnections Performing Applications With Task Dependencies

Current System-on-Chips (SoCs) execute applications with task dependency that compete for shared resources such as buses, memories, and accelerators. In such a structure, the arbitration policy becomes a critical part of the system to guarantee access and bandwidth suitable for the competing applications. Some strategies proposed in the literature to cope with these issues are Round-Robin, Weighted Round-Robin, Lottery, Time Division Access Multiplexing (TDMA), and combinations. However, a fine-grained bandwidth control arbitration policy is missing from the literature. We propose an innovative arbitration policy based on opportunistic access and a supervised utilization of the bus in terms of transmitted flits (transmission units) that settle the access and fine-grained control. In our proposal, every competing element has a budget. Opportunistic access grants the bus to request even if the component has spent all its flits. Supervised debt accounts a record for every transmitted flit when it has no flits to spend. Our proposal applies to interconnection systems such as buses, switches, and routers. The presented approach achieves deadlock-free behavior even with task dependency applications in the scenarios analyzed through cycle-accurate simulation models. The synergy between opportunistic and supervised debt techniques outperforms Lottery, TDMA, and Weighted Round-Robin in terms of bandwidth control in the experimental studies performed

Integrated voice/data through a digital PBX

The digital voice/data PBX is finally reaching its anticipated potential and becoming a major factor when considering the total communications picture for many businesses today. The digital PBX has always been the choice for voice communications but has lagged behind the LAN industry when it comes to data transfers. The pendulum has begun to swing with the enhanced data capabilities of third and fourth generation PBXs. The battle for the total communication market is quite fierce between the LAN and PBX vendors now. This research thesis looks at the history, evolution, and architecture of voice/data PBXs. It traces development of PBXs through the present fourth generation architectures. From the first manual switches introduced in the late 1800\u27s through the Strowger switch, step-by-step switching, stored program control, common control, digital switches, dual bus architectures, and finally what is anticipated in the future. A detailed description of the new fourth generation dual bus architectures is presented. Lastly, speculations on the future direction PBX architectures will take is explored. A description of the mechanics of a possible Wave Division PBX is presented based on a fiber optic transport system