The integrity of serial data highway systems

The Admiralty Surface Weapons Establishment (ASWE) have developed a Local Area Network System. This thesis describes the development of a replacement for this LAN system, based around 16 bit microprocessor hosts, as opposed to the minicomputers currently used. This change gave a substantial reduction in size, and allowed the new system to be installed on a ship and tested under operational conditions. Analysis of the data collected during the tests gave performance information on the ASWE system. The performance of this LAN is compared to that of other leading types of LAN. The design of a portable network controller/ monitor unit is presented, which may be manufactured as a standard controller for the ASWE Serial Highway

A Parallel Processor System for Nuclear Shell-Model Calculations

This thesis describes the design and implementation of a dedicated parallel processor system for nuclear shell-model calculations. The purpose of these calculations is to determine nuclear energy eigenvalues by the tridiagonalisation of the nuclear Hamiltonian matrix using the Lanczos method. The Theoretical Nuclear Structure group at Glasgow University's Physics Department would normally perform this type of calculation on a high-performance main-frame computer. However these machines have limitations which restrict the number and scope of the calculations that can be performed. The Shell Model Processor system consists of a Multiple Microprocessor Unit (MMPU) driven by a highly pipelined dedicated front-end processor. The MMPU has a modular, moderately coupled, MIMD architecture based on autonomous processing modules. The elements within the system communicate via three shared buses. The front-end is responsible for determining the position of non-zero elements within the Hamiltonian matrix. Once the position of an element has been found it is passed to one of the free processing modules within the MMPU. The processing module then determines the value of the matrix element and performs the appropriate arithmetic to accumulate the resultant Lanczos vector. Two such processing modules have been developed. The most recently developed module is based on two MC68000 16/32 bit microprocessors. In addition there are two supervisory processor modules, one of which controls the front-end and also assists it in its function. The other module has privileged system capabilities and is responsible for supervising the system as a whole. The system has been successfully tested and performance figures are presented. The future expansion of the system to allow it to perform larger calculations is also discussed

Using FPGAs to prototype a self-timed floating point co-processor

Journal ArticleSelf- timed circuits offer advantages over their synchronously clocked counterparts in a number of situations. However, self-timed design techniques are not widely used at present for a variety of reasons. One reason for the lack of experimentation with self-timed systems is the lack of commercially available parts to support this style of design. Field programmable gate arrays (FPGAs) offer an excellent alternative for the rapid development of novel system designs provided suitable circuit structures can be implemented. This paper describes a self-timed floating point co-processor built using a combination of Actel Field Programmable Gate Arrays (FPGAs) and semi-custom CMOS chips. This co-processor implements IEEE standard single precision floating point operations on 32-bit values. The control is completely self-timed. Data moves between parts of the circuit according to local constraints only: there is no global clock or global control circuit

Power system optimisation and stability studies using real-time simulation

SIGLEAvailable from British Library Document Supply Centre- DSC:D68146/86 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

An experimental design framework for evolutionary robotics

Based on the failures of work in the area of machine intelligence in the past, a new paradigm has been proposed: for a machine to develop intelligence it should be able to interact with and survive within a hostile dynamic environment. It should therefore be able to display adaptive behaviour and respond correctly to changes in its situation. This means that before higher cognitive properties can be modeled, the modeling of the lower levels of intelligence would be achieved first. Only by building on this platform of physical and mental abilities may it be possible to develop true intelligence. One train of thought for implementing this is to control and design a robot by modeling the neuroethology of simpler animals such as insects. This thesis outlines one approach to the design and development of such a robot, controlled by a neural network, by combining the work of a number of researchers in the areas of machine intelligence and artificial life. It involves Rodney Brooks’ subsumption architecture, Randall D. Beer’s work in the area of computational neuroethology, Richard Dawkins’ work in the area of biomorphs and computational embryology and finally the work of John Holland and David Goldberg in genetic algorithms. This thesis will demonstrate the method and reasoning behind the combination of the work of the above named researchers. It will also detail and analyse the results obtained by their application