Exploration Games:Can Game-Guided Systems Support Users in Automated Exhibition Sites?

This article delves into the potential of incorporating elements fromadventure games into museum exhibitions, with a particular focus on automatedexhibition sites. We advocate that principles derived from adventure games canadeptly bridge the two primary expectations of exhibitions: enlightenment andexperience. Exploration-based games, such as Explore the Redoubt (XTR)crafted for automated venues, enable users to fulfill both these objectives. XTR,conceived to address the prevailing research voids, integrates game mechanicsinto the automated exhibition environment, enhancing visitor motivation andengagement. It harnesses interactive digital mediums to present cultural heritagein a relaxed, informal manner.Existing research scarcely touches upon the design of experiential learninggames developed for automated sites, which encompass both indoor and outdoordisplays. Our methodology contemplates the transformation of visitor conduct atexhibitions, morphing them into avid knowledge seekers. We challenge theadequacy of current user experience models in portraying exhibitions striving toprovide both enlightenment and an immersive experience. Consequently, weintroduce a framework for museum interactions that deeply engages users, urgingthem to define their exploration trajectories, seamlessly fusing enlightenment,and engagement. Our study is set in a 17th-century redoubt where initialobservations indicated greater outdoor engagement compared to indoor spaces.This observation fueled our initiative to amplify indoor visitor participation.After testing XTR with 30 participants and employing a combination ofobservations and interviews, we derived key insights on designing digitalexploration games that seamlessly combine enlightenment and engagement. Weconclude with three design strategies to enhance visitor curiosity and exploration

Square dancing: official magazine of the Sets in Order American Square Dance Society.

Published monthly for and by Square Dancers

Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip

The sustained demand for faster, more powerful chips has been met by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the onchip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation performs a design space exploration of network-on-chip architectures, in order to point-out the trade-offs associated with the design of each individual network building blocks and with the design of network topology overall. The design space exploration is preceded by a comparative analysis of state-of-the-art interconnect fabrics with themselves and with early networkon- chip prototypes. The ultimate objective is to point out the key advantages that NoC realizations provide with respect to state-of-the-art communication infrastructures and to point out the challenges that lie ahead in order to make this new interconnect technology come true. Among these latter, technologyrelated challenges are emerging that call for dedicated design techniques at all levels of the design hierarchy. In particular, leakage power dissipation, containment of process variations and of their effects. The achievement of the above objectives was enabled by means of a NoC simulation environment for cycleaccurate modelling and simulation and by means of a back-end facility for the study of NoC physical implementation effects. Overall, all the results provided by this work have been validated on actual silicon layout

American Square Dance Vol. 38, No. 2 (Feb. 1983)

Monthly square dance magazine that began publication in 1945

Square dancing: the official magazine of the Sets in Order American Square Dance Society.

Published monthly for and by Square Dancers and for the general enjoyment of all

Sets in Order: the official magazine of square dancing.

Published monthly for and by Square Dancers and for the general enjoyment of all

Square dancing: the official magazine of the Sets in Order American Square Dance Society.

Published monthly for and by Square Dancers and for the general enjoyment of all

Square dancing: official magazine of the Sets in Order American Square Dance Society.

Published monthly for and by Square Dancers and for the general enjoyment of all

Square dancing: official magazine of the Sets in Order American Square Dance Society.

Published monthly for and by Square Dancers and for the general enjoyment of all

Exploration and Design of Power-Efficient Networked Many-Core Systems

Multiprocessing is a promising solution to meet the requirements of near future applications. To get full benefit from parallel processing, a manycore system needs efficient, on-chip communication architecture. Networkon- Chip (NoC) is a general purpose communication concept that offers highthroughput, reduced power consumption, and keeps complexity in check by a regular composition of basic building blocks. This thesis presents power efficient communication approaches for networked many-core systems. We address a range of issues being important for designing power-efficient manycore systems at two different levels: the network-level and the router-level. From the network-level point of view, exploiting state-of-the-art concepts such as Globally Asynchronous Locally Synchronous (GALS), Voltage/ Frequency Island (VFI), and 3D Networks-on-Chip approaches may be a solution to the excessive power consumption demanded by today’s and future many-core systems. To this end, a low-cost 3D NoC architecture, based on high-speed GALS-based vertical channels, is proposed to mitigate high peak temperatures, power densities, and area footprints of vertical interconnects in 3D ICs. To further exploit the beneficial feature of a negligible inter-layer distance of 3D ICs, we propose a novel hybridization scheme for inter-layer communication. In addition, an efficient adaptive routing algorithm is presented which enables congestion-aware and reliable communication for the hybridized NoC architecture. An integrated monitoring and management platform on top of this architecture is also developed in order to implement more scalable power optimization techniques. From the router-level perspective, four design styles for implementing power-efficient reconfigurable interfaces in VFI-based NoC systems are proposed. To enhance the utilization of virtual channel buffers and to manage their power consumption, a partial virtual channel sharing method for NoC routers is devised and implemented. Extensive experiments with synthetic and real benchmarks show significant power savings and mitigated hotspots with similar performance compared to latest NoC architectures. The thesis concludes that careful codesigned elements from different network levels enable considerable power savings for many-core systems.Siirretty Doriast