A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals

A Field Programmable Sequencer and Memory (FPSM), which is a programmable unit exclusively optimized for peripherals on a micro controller unit, is proposed. The FPSM functions as not only the peripherals but also the standard built-in memory. The FPSM provides easier programmability with a smaller area overhead, especially when compared with the FPGA. The FPSM is implemented on the FPGA and the programmability and performance for basic peripherals such as the 8 bit counter and 8 bit accuracy Pulse Width Modulation are emulated on the FPGA. Furthermore, the FPSM core with a 4K bit SRAM is fabricated in 0.18µm 5 metal CMOS process technology. The FPSM is an half the area of FPGA, its power consumption is less than one-fifth.Embargo Period 6 month

High Speed Clock Glitching

In recent times, hardware security has drawn a lot of interest in the research community. With physical proximity to the target devices, various fault injection hardware attack methods have been proposed and tested to alter their functionality and trigger behavior not intended by the design. There are various types of faults that can be injected depending on the parameters being used and the level at which the device is tampered with. The literature describes various fault models to inject faults in clock of the target but there are no publications on overclocking circuits for fault injection. The proposed method bridges this gap by conducting high-speed clock fault injection on latest high-speed micro-controller units where the target device is overclocked for a short duration in the range of 4-1000 ns. This thesis proposes a method of generating a high-speed clock and driving the target device using the same clock. The properties of the target devices for performing experiments in this research are: Externally accessible clock input line and GPIO line. The proposed method is to develop a high-speed clock using custom bit-stream sent to FPGA and subsequently using external analog circuitry to generate a clock-glitch which can inject fault on the target micro-controller. Communication coupled with glitching allows us to check the target\u27s response, which can result in information disclosure.This is a form of non-invasive and effective hardware attack. The required background, methodology and experimental setup required to implement high-speed clock glitching has been discussed in this thesis. The impact of different overclock frequencies used in clock fault injection is explored. The preliminary results have been discussed and we show that even high-speed micro-controller units should consider countermeasures against clock fault injection. Influencing the execution of Tiva C Launchpad and STM32F4 micro-controller units has been shown in this thesis. The thesis details the method used for the testing a

Development of PCI Embedded Card Useful for Microcontroller Trainer

Not availabl

Feasibility study for a numerical aerodynamic simulation facility. Volume 2: Hardware specifications/descriptions

An FMP (Flow Model Processor) was designed for use in the Numerical Aerodynamic Simulation Facility (NASF). The NASF was developed to simulate fluid flow over three-dimensional bodies in wind tunnel environments and in free space. The facility is applicable to studying aerodynamic and aircraft body designs. The following general topics are discussed in this volume: (1) FMP functional computer specifications; (2) FMP instruction specification; (3) standard product system components; (4) loosely coupled network (LCN) specifications/description; and (5) three appendices: performance of trunk allocation contention elimination (trace) method, LCN channel protocol and proposed LCN unified second level protocol

Feasibility study for a numerical aerodynamic simulation facility. Volume 1

A Numerical Aerodynamic Simulation Facility (NASF) was designed for the simulation of fluid flow around three-dimensional bodies, both in wind tunnel environments and in free space. The application of numerical simulation to this field of endeavor promised to yield economies in aerodynamic and aircraft body designs. A model for a NASF/FMP (Flow Model Processor) ensemble using a possible approach to meeting NASF goals is presented. The computer hardware and software are presented, along with the entire design and performance analysis and evaluation

Digital System Design - Use of Microcontroller

Embedded systems are today, widely deployed in just about every piece of machinery from toasters to spacecraft. Embedded system designers face many challenges. They are asked to produce increasingly complex systems using the latest technologies, but these technologies are changing faster than ever. They are asked to produce better quality designs with a shorter time-to-market. They are asked to implement increasingly complex functionality but more importantly to satisfy numerous other constraints. To achieve the current goals of design, the designer must be aware with such design constraints and more importantly, the factors that have a direct effect on them.One of the challenges facing embedded system designers is the selection of the optimum processor for the application in hand; single-purpose, general-purpose or application specific. Microcontrollers are one member of the family of the application specific processors.The book concentrates on the use of microcontroller as the embedded system?s processor, and how to use it in many embedded system applications. The book covers both the hardware and software aspects needed to design using microcontroller.The book is ideal for undergraduate students and also the engineers that are working in the field of digital system design.Contents• Preface;• Process design metrics;• A systems approach to digital system design;• Introduction to microcontrollers and microprocessors;• Instructions and Instruction sets;• Machine language and assembly language;• System memory; Timers, counters and watchdog timer;• Interfacing to local devices / peripherals;• Analogue data and the analogue I/O subsystem;• Multiprocessor communications;• Serial Communications and Network-based interfaces

Edge of the network device for a low power wide area network

Dissertação de mestrado em Engenharia Eletrónica Industrial e ComputadoresThe widespread of Internet connection, particularly on small devices (embedded systems), has allowed the development of the Internet of Things (IoT) concept, due to the connection of these devices to web micro services (Cloud), and has had a major role in Industry 4.0 [1]. Through the advances of wireless technologies, these devices were able to have an Internet connection, becoming available everywhere. The creation of Wireless Sensor Networks (WSNs) has enabled the use of networks composed of independent devices (nodes or edge devices), equipped with sensors and actuators, and made it possible to collect information about the environment where they are deployed [2]. The growing necessity of having a wider coverage area for Wireless Sensor Networks, along with the demanding low power requirements on devices has enabled Low Power Wide Area (LPWA) technologies to arise. These technologies are able to reach further coverage than conventional wireless technologies (such as Bluetooth, Wi-Fi, ZigBee etc), as well as raising the energy autonomy of the devices [3], which makes LPWA technologies ideal for wider areas. The recent tragedies of wildfires in Portugal, in both 2017 and 2018, had great impact on economic and social levels. Early detection and alerts about wildfires are crucial to prevent them from spreading [4]. Therefore, by using LPWA technologies in forests, a case study can be made for the wildfire occurrences in forests. Through the use of independent devices equipped with sensors, data can be collected from the environment that might detect that a fire is starting, and then send alerts to fire fighting units. In this Master’s thesis it was developed the architecture of sensor nodes, to be integrated in a Low Power Wide Area Network (LPWAN). By using the LoRa technology to achieve a long range between the sensor nodes and the network coordinator, it is possible for edge devices to collect and send data to upper levels of the network. It was possible to gather information about the environment and further understand LoRa’s potential for sending all the data to the upper levels of the network.A proliferação da conexão à Internet, especialmente em pequenos dispositivos (sistemas embebidos), permitiu o desenvolvimento do conceito Internet of Things (IoT), devido à possibilidade de ligação destes a micro serviços web (Cloud), tendo um papel crucial no desenrolar da Indústria 4.0 [1]. Tendo como principal impulsionador o avanço tecnológico das redes sem fios, foi possível ligar estes dispositivos à Internet, tornando-os acessíveis em qualquer lado. Assim, surgiram as Wireless Sensor Networks (WSNs), através da utilização de redes de dispositivos independentes (nós ou edge devices), equipados com sensores e atuadores, possibilitando a recolha de informação sobre o meio onde estão colocados [2]. A crescente necessidade de cobrir áreas cada vez maiores para este tipo de redes, associada a requisitos mais exigentes de consumo energético reduzido nos dispositivos, abriu caminho para o aparecimento das tecnologias Low Power Wide Area (LPWA). Este tipo de tecnologias consegue alcances superiores em relação às redes sem fios convencionais (Wi-Fi, Bluetooth, entre outros), permitindo maior autonomia dos nós sensores [3], tornando-se assim ideais para a sua utilização em áreas alargadas. As recentes tragédias de incêndios que ocorreram em Portugal, em particular nos anos de 2017 e 2018, tiveram grande impacto tanto a nível económico como social. A deteção e alerta precoce de incêndios são fatores cruciais para evitar a sua propagação [4]. Utilizando as tecnologias LPWA em contexto florestal poderá criar-se um caso de estudo para a ocorrência de incêndios em florestas. Através da utilização de edge devices, poderá ser possível recolher dados provenientes deste meio que indiquem a existência de um incêndio a deflagrar, e enviar alertas para as unidades de combate a incêndios. Nesta dissertação foi desenvolvida a arquitetura dos nós sensores, a serem integrados numa Low Power Wide Area Network (LPWAN). Utilizando tecnologia LoRa para obter um longo alcance entre os nós e o coordenador da rede, poderá desta forma ser possível os nós sensores recolherem e enviarem dados para as camadas superiores. Foi possível, com a utilização de sensores nos nós, recolher informações sobre o ambiente e perceber o potencial da tecnologia LoRa para o envio destes dados para as camadas superiores

メモリをベースとしたマイコン用再構成可能デバイスとその応用に関する研究

13301甲第4625号博士（工学）金沢大学博士論文本文Ful