A floating-point/multiple-precision processor for airborne applications

A compact input output (I/O) numerical processor capable of performing floating-point, multiple precision and other arithmetic functions at execution times which are at least 100 times faster than comparable software emulation is described. The I/O device is a microcomputer system containing a 16 bit microprocessor, a numerical coprocessor with eight 80 bit registers running at a 5 MHz clock rate, 18K random access memory (RAM) and 16K electrically programmable read only memory (EPROM). The processor acts as an intelligent slave to the host computer and can be programmed in high order languages such as FORTRAN and PL/M-86

Parallel Processing of the Fast Fourier Transform

The first FFT algorithms were reported by Runge and Konig in 1924, and by Danielson and Lanczos in 1942. However, the FFT didn\u27t receive much attention at all until Cooley and Tukey published their algorithm in 1965. The Cooley-Tukey algorithm is simple and widely used in many application software packages. Winograd developed his FFT in 1976, which is based upon the prime factor theory. It is typically faster than the Cooley-Tukey Algorithm, if the computer system has no multiplication instructions. According to the book prepared by the Digital Signal Processing Committee of the IEEE in 1979, the speed difference among these FFT algorithms is around 40%. My objective in this paper is to choose a proper algorithm, establish the appropriate programming techniques, and determine the sequence of steps required to implement a FFT both on a conventional IBM-PC and a Vector Processor (VP) system. I will demonstrate how to vectorize a FFT so that the algorithm can be performed under a VP system. The analysis of data dependence in an algorithm is another important part of this paper. The paper includes the analysis of the Cooley-Tukey and Winograd FFT algorithms. The Prime factor method will be used in these two FFTs. It will be seen that the Cooley-Tukey Algorithm can be more easily implemented on a vector system and needs fewer memory locations. The details of\u27 the Winograd FFT algorithm can be found in. In addition, this paper has two Cooley-Tukey FFTs and one DFT program written in Assembly Language. One of two FFT programs has been tested and executed on a conventional IBM-PC which has an Intel-8088 processor as the Central Processing Unit, and one Intel-8087 Numeric Data Processor. The 8087 is specially designed to perform real number operations efficiently and quickly. Because of the special architecture of the 8087, single or double precision can be easily processed. The tested program was compiled and linked by Microsoft Assembly Language version 5.0 and the required results of both the FFT and Inverse FFT were obtained

A Spacecraft Computer for High-Performance Applications

A high-performance processor circuit called the SC-3 has been developed to meet the requirements of advanced experiment and attitude control applications. It is based on the 16 MHz Intel 80386/80387 chip set and implements a dual bus system configuration which allows high-speed, 32-bit wide memory and low-speed. 16-bit wide Input Output(I/O) circuits to be separated. This separation maintains compatibility with a wide range of current I/O circuit designs while exploiting the high-bandwidth memory access capabilities of the 80386. Performance is further enhanced by means of a cache on the 32-bit bus. Gibson, Whetstone, and Dhrystone instruction mixes have been used to evaluate performance under various operating modes. When the SC-3 is constrained to execute from 16-bit memory. the Gibson mix indicates a 32% performance improvement compared to previous 16-bit processors. An average of 1.1 million Whetstones per second are performed over the typical range of memory wait states. The average Dhrystone performance improvement between 32-bit non-cached and 32-bit cached operation over a typical range of memory wait states is 115%. The initial application of this processor circuit is on Stanford University\u27s Gravity Probe-B experiment

Software development for the VLA-GDSCC telemetry array project

Software for the VLA-GDSCC Telemetry Array (VGTA) Project is being developed in a new manner. Within the Radio Frequency and Microwave Subsystems Section, most microprocessor software has been developed using Intel hardware and software development systems. The VGTA software, however, is being developed using IBM PCs running consumer-oriented software. Utility software and procedures have been generated which allow the software developed on the IBM PCs to be transferred and run on a multibus 8086 computer

Multiprocessor design for real-time embedded systems

Multiprocessor design for real-time embedded system

Design of a microprocessor-based Control, Interface and Monitoring (CIM unit for turbine engine controls research

High speed minicomputers were used in the past to implement advanced digital control algorithms for turbine engines. These minicomputers are typically large and expensive. It is desirable for a number of reasons to use microprocessor-based systems for future controls research. They are relatively compact, inexpensive, and are representative of the hardware that would be used for actual engine-mounted controls. The Control, Interface, and Monitoring Unit (CIM) contains a microprocessor-based controls computer, necessary interface hardware and a system to monitor while it is running an engine. It is presently being used to evaluate an advanced turbofan engine control algorithm

The RANDOM computer program: A linear congruential random number generator

The RANDOM Computer Program is a FORTRAN program for generating random number sequences and testing linear congruential random number generators (LCGs). The linear congruential form of random number generator is discussed, and the selection of parameters of an LCG for a microcomputer described. This document describes the following: (1) The RANDOM Computer Program; (2) RANDOM.MOD, the computer code needed to implement an LCG in a FORTRAN program; and (3) The RANCYCLE and the ARITH Computer Programs that provide computational assistance in the selection of parameters for an LCG. The RANDOM, RANCYCLE, and ARITH Computer Programs are written in Microsoft FORTRAN for the IBM PC microcomputer and its compatibles. With only minor modifications, the RANDOM Computer Program and its LCG can be run on most micromputers or mainframe computers

Power System Simulation by Parallel Computation

The concept of parallel processing is applied to power system simulation. The Component Connection Model (CCM) and appropriate numerical methods, such as the Relaxation Algorithm, are established as a conceptual basis for the parallel simulation of small power networks and individual power system components. A commercially available multiprocessing system is introduced for the power system simulator, and the system is adapted to facilitate high-speed parallel simulations. Two separate strategies for controlling the parallel simulation, synchronous and asynchronous relaxation, are introduced, and their performances are evaluated for the parallel simulation of an induction motor drive system. The performances of the parallel methods are also compared to a similar simulation run on a single processor, and the results show that considerable simulation speed-up can be obtained when parallel processing is employed

Digital Filtering with the iAPX 86/20

The iAPX 86/20 (8086 with the 8087 numeric coprocessor) is considered for digital filtering. The advantage in using the iAPX 86/20 lies in the 80-bit width of the 8087 floating-point arithmetic-registers. With such large arithmetic registers, the effects of coefficient roundoff and arithmetic roundoff errors on the filter output are reduced. The price paid for the improved numerical performance is the increased time spent by the system moving data to and from memory. The method of Knowles and Olcayto for measuring the effect of coefficient roundoff is studies in detail. This method is applied to an example filter in order to demonstrate that the iAPX 86/20 can meet filter specifications that the 8086 without the numeric coprocessor (iAPX 86/10) cannot meet