Tunable Balun Low-Noise Amplifier in 65nm CMOS Technology

The presented paper includes the design and implementation of a 65 nm CMOS low-noise amplifier (LNA) based on inductive source degeneration. The amplifier is realized with an active balun enabling a single-ended input which is an important requirement for low-cost system on chip implementations. The LNA has a tunable bandpass characteristics from 4.7 GHz up to 5.6 GHz and a continuously tunable gain from 22 dB down to 0 dB, which enables the required flexibility for multi-standard, multi-band receiver architectures. The gain and band tuning is realized with an optimized tunable active resistor in parallel to a tunable L-C tank amplifier load. The amplifier achieves an IIP3 linearity of -8dBm and a noise figure of 2.7 dB at the highest gain and frequency setting with a low power consumption of 10 mW. The high flexibility of the proposed LNA structure together with the overall good performance makes it well suited for future multi-standard low-cost receiver front-ends

Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS

In questo lavoro si presenta una metodologia di progettazione elettronica a livello di sistema, affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di equazioni atti a selezionare le configurazione di interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre, il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso

A VHDL-AMS Simulation Environment for an UWB Impulse Radio Transceiver

Ultra-Wide-Band (UWB) communication based on the impulse radio paradigm is becoming increasingly popular. According to the IEEE 802.15 WPAN Low Rate Alternative PHY Task Group 4a, UWB will play a major role in localization applications, due to the high time resolution of UWB signals which allow accurate indirect measurements of distance between transceivers. Key for the successful implementation of UWB transceivers is the level of integration that will be reached, for which a simulation environment that helps take appropriate design decisions is crucial. Owing to this motivation, in this paper we propose a multiresolution UWB simulation environment based on the VHDL-AMS hardware description language, along with a proper methodology which helps tackle the complexity of designing a mixed-signal UWB System-on-Chip. We applied the methodology and used the simulation environment for the specification and design of an UWB transceiver based on the energy detection principle. As a by-product, simulation results show the effectiveness of UWB in the so-called ranging application, that is the accurate evaluation of the distance between a couple of transceivers using the two-way-ranging metho

An effective AMS Top-Down Methodology Applied to the Design of a Mixed-SignalUWB System-on-Chip

The design of Ultra Wideband (UWB) mixed-signal SoC for localization applications in wireless personal area networks is currently investigated by several researchers. The complexity of the design claims for effective top-down methodologies. We propose a layered approach based on VHDL-AMS for the first design stages and on an intelligent use of a circuit-level simulator for the transistor-level phase. We apply the latter just to one block at a time and wrap it within the system-level VHDL-AMS description. This method allows to capture the impact of circuit-level design choices and non-idealities on system performance. To demonstrate the effectiveness of the methodology we show how the refinement of the design affects specific UWB system parameters such as bit-error rate and localization estimations

Analysis and Design of Wideband Low Noise Amplifier with Digital Control

The design issues in designing low noise amplifier (LNA) for Software-Defined-Radio (SDR) are reviewed. An inductor-less wideband low noise amplifier aiming at low frequency band (0.2-2GHz) for Software-Defined-Radio is presented. Shunt-shunt LNA with active feedback is used as the first stage which is carefully optimized for low noise and wide band applications. A digitally controlled second stage is employed to provide an additional 12dB gain control. A novel method is proposed to bypass the first stage without degrading input matching. This LNA is fabricated in a standard 0.18 um CMOS technology. The measurement result shows the proposed LNA has a gain range of 6dB-18dB at high gain mode and -12dB-0dB at low gain mode, as well as a –3dB bandwidth of 2GHz. The noise figure (NF) is 3.5-4.5dB in the high gain setting mode. It consumes 20mW from a 1.8V supply

A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5° and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB

Energy-Aware Low-Power CMOS LNA with Process-Variations Management

A reconfigurable low-noise amplifier (LNA) with digitally controllable gain and power consumption is presented.This architecture allows increasing power consumption only when required, that is, to improve LNA’s radiofrequency performance at extreme communication-channel conditions and/or to counteract the effect of process, voltage, and temperature variations.The proposed design leads to significant power saving when a relaxed operation is acceptable. The LNA is implemented in a 130nm 1.2V CMOS technology for a 2.4GHz IEEE-802.15.4 application. Simulated LNAperformance (taking into account theworst cases under process variations) is comparable to recently published worksCAPES-Brazil 176/12Ministerio de Asuntos Exteriores y Cooperación D/024124/09Junta de Andalucía P09-TIC- 5386Ministerio de Economía y Competitividad TEC2011-2830

A handheld high-sensitivity micro-NMR CMOS platform with B-field stabilization for multi-type biological/chemical assays

We report a micro-nuclear magnetic resonance (NMR) system compatible with multi-type biological/chemical lab-on-a-chip assays. Unified in a handheld scale (dimension: 14 x 6 x 11 cm³, weight: 1.4 kg), the system is capable to detect<100 pM of Enterococcus faecalis derived DNA from a 2.5 μL sample. The key components are a portable magnet (0.46 T, 1.25 kg) for nucleus magnetization, a system PCB for I/O interface, an FPGA for system control, a current driver for trimming the magnetic (B) field, and a silicon chip fabricated in 0.18 μm CMOS. The latter, integrated with a current-mode vertical Hall sensor and a low-noise readout circuit, facilitates closed-loop B-field stabilization (2 mT → 0.15 mT), which otherwise fluctuates with temperature or sample displacement. Together with a dynamic-B-field transceiver with a planar coil for micro-NMR assay and thermal control, the system demonstrates: 1) selective biological target pinpointing; 2) protein state analysis; and 3) solvent-polymer dynamics, suitable for healthcare, food and colloidal applications, respectively. Compared to a commercial NMR-assay product (Bruker mq-20), this platform greatly reduces the sample consumption (120x), hardware volume (175x), and weight (96x)

Characterization of 28 nm FDSOI MOS and application to the design of a low-power 2.4 GHz LNA

IoT is expected to connect billions of devices all over world in the next years, and in a near future, it is expected to use LR-WPAN in a wide variety of applications. Not all the devices will require of high performance but will require of low power hungry systems since most of them will be powered with a battery. Conventional CMOS technologies cannot cover these needs even scaling it to very small regimes, which appear other problems. Hence, new technologies are emerging to cover the needs of this devices. One promising technology is the UTBB FDSOI, which achieves good performance with very good energy efficiency. This project characterizes this technology to obtain a set of parameters of interest for analog/RF design. Finally, with the help of a low-power design methodology (gm/Id approach), a design of an ULP ULV LNA is performed to check the suitability of this technology for IoT