3,322 research outputs found
Redundant Logic Insertion and Fault Tolerance Improvement in Combinational Circuits
This paper presents a novel method to identify and insert redundant logic
into a combinational circuit to improve its fault tolerance without having to
replicate the entire circuit as is the case with conventional redundancy
techniques. In this context, it is discussed how to estimate the fault masking
capability of a combinational circuit using the truth-cum-fault enumeration
table, and then it is shown how to identify the logic that can introduced to
add redundancy into the original circuit without affecting its native
functionality and with the aim of improving its fault tolerance though this
would involve some trade-off in the design metrics. However, care should be
taken while introducing redundant logic since redundant logic insertion may
give rise to new internal nodes and faults on those may impact the fault
tolerance of the resulting circuit. The combinational circuit that is
considered and its redundant counterparts are all implemented in semi-custom
design style using a 32/28nm CMOS digital cell library and their respective
design metrics and fault tolerances are compared
Digital IP Protection Using Threshold Voltage Control
This paper proposes a method to completely hide the functionality of a
digital standard cell. This is accomplished by a differential threshold logic
gate (TLG). A TLG with inputs implements a subset of Boolean functions of
variables that are linear threshold functions. The output of such a gate is
one if and only if an integer weighted linear arithmetic sum of the inputs
equals or exceeds a given integer threshold. We present a novel architecture of
a TLG that not only allows a single TLG to implement a large number of complex
logic functions, which would require multiple levels of logic when implemented
using conventional logic primitives, but also allows the selection of that
subset of functions by assignment of the transistor threshold voltages to the
input transistors. To obfuscate the functionality of the TLG, weights of some
inputs are set to zero by setting their device threshold to be a high .
The threshold voltage of the remaining transistors is set to low to
increase their transconductance. The function of a TLG is not determined by the
cell itself but rather the signals that are connected to its inputs. This makes
it possible to hide the support set of the function by essentially removing
some variable from the support set of the function by selective assignment of
high and low to the input transistors. We describe how a standard cell
library of TLGs can be mixed with conventional standard cells to realize
complex logic circuits, whose function can never be discovered by reverse
engineering. A 32-bit Wallace tree multiplier and a 28-bit 4-tap filter were
synthesized on an ST 65nm process, placed and routed, then simulated including
extracted parastics with and without obfuscation. Both obfuscated designs had
much lower area (25%) and much lower dynamic power (30%) than their
nonobfuscated CMOS counterparts, operating at the same frequency
Combinational Circuit Obfuscation through Power Signature Manipulation
Today\u27s military systems are composed of hardware and software systems, many of which are critical technologies, and must be protected to ensure our adversaries cannot gain any information from a various analysis attacks. Side Channel Analysis (SCA) attacks allow an attacker to gain the significant information from the measured signatures leaked by side-channels such as power consumption, and electro-magnetic emission. In this research the focus on detecting, characterizing, and manipulating the power signature by designing a power signature estimation and manipulation method. This research has determined that the proposed method capable of characterizing and altering the type of power signature can provide a protection against adversarial SCA attacks
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Using a genetic algorithm for optimizing the functional decomposition of multiple-valued functions
The genetic algorithm which determines the good functional decomposition of multiple-valued logic functions is presented. The algorithm expands the range of searching for a best decomposition, providing the optimal column multiplicity. The possible solutions are evaluated using the gain of decomposition for multiple-valued function
Technology Mapping for Circuit Optimization Using Content-Addressable Memory
The growing complexity of Field Programmable Gate Arrays (FPGA's) is leading to architectures with high input cardinality look-up tables (LUT's). This thesis describes a methodology for area-minimizing technology mapping for combinational logic, specifically designed for such FPGA architectures. This methodology, called LURU, leverages the parallel search capabilities of Content-Addressable Memories (CAM's) to outperform traditional mapping algorithms in both execution time and quality of results. The LURU algorithm is fundamentally different from other techniques for technology mapping in that LURU uses textual string representations of circuit topology in order to efficiently store and search for circuit patterns in a CAM. A circuit is mapped to the target LUT technology using both exact and inexact string matching techniques. Common subcircuit expressions (CSE's) are also identified and used for architectural optimization---a small set of CSE's is shown to effectively cover an average of 96% of the test circuits. LURU was tested with the ISCAS'85 suite of combinational benchmark circuits and compared with the mapping algorithms FlowMap and CutMap. The area reduction shown by LURU is, on average, 20% better compared to FlowMap and CutMap. The asymptotic runtime complexity of LURU is shown to be better than that of both FlowMap and CutMap
A survey of an introduction to fault diagnosis algorithms
This report surveys the field of diagnosis and introduces some of the key algorithms and heuristics currently in use. Fault diagnosis is an important and a rapidly growing discipline. This is important in the design of self-repairable computers because the present diagnosis resolution of its fault-tolerant computer is limited to a functional unit or processor. Better resolution is necessary before failed units can become partially reuseable. The approach that holds the greatest promise is that of resident microdiagnostics; however, that presupposes a microprogrammable architecture for the computer being self-diagnosed. The presentation is tutorial and contains examples. An extensive bibliography of some 220 entries is included
Deterministic, Efficient Variation of Circuit Components to Improve Resistance to Reverse Engineering
This research proposes two alternative methods for generating semantically equivalent circuit variants which leave the circuit\u27s internal structure pseudo-randomly determined. Component fusion deterministically selects subcircuits using a component identification algorithm and replaces them using a deterministic algorithm that generates canonical logic forms. Component encryption seeks to alter the semantics of individual circuit components using an encoding function, but preserves the overall circuit semantics by decoding signal values later in the circuit. Experiments were conducted to examine the performance of component fusion and component encryption against representative trials of subcircuit selection-and-replacement and Boundary Blurring, two previously defined methods for circuit obfuscation. Overall, results support the conclusion that both component fusion and component encryption generate more secure variants than previous methods and that these variants are more efficient in terms of required circuit delay and the power and area required for their implementation
Dynamic Field Programmable Logic-Driven Soft Exosuit
The next generation of etextiles foresees an era of smart wearable garments
where embedded seamless intelligence provides the ability to sense, process and
perform. Core to this vision is embedded textile functionality enabling dynamic
configuration. In this paper we detail a methodology, design and implementation
of a dynamic field programmable logic-driven fabric soft exosuit. Dynamic field
programmability allows the soft exosuit to alter its functionality and adapt to
specific exercise programs depending on the wearers need. The dynamic field
programmability is enabled through motion based control arm movements of the
soft exosuit triggering momentary sensors embedded in the fabric exosuit at
specific joint placement points (right arm: wrist, elbow).The embedded
circuitry in the fabric exosuit is implemented using a layered and
interchangeable approach. This includes logic gate patches (AND,OR,NOT) and a
layered textile interconnection panel. This modular and interchangeable design
enhances the soft exosuits flexibility and adaptability. A truth table aligning
to a rehabilitation healthcare use case was utilised. Tests were completed
validating the field programmability of the soft exosuit and its capability to
switch between its embedded logic driven circuitry and its operational and
functionality options controlled by motion movement of the wearers right arm
(elbow and wrist). Iterative exercise movement and acceleration based tests
were completed to validate the functionality of the field programmable logic
driven fabric exosuit. We demonstrate a working soft exosuit prototype with
motion controlled operational functionality that can be applied to
rehabilitation applications.Comment: 20 pages, 9 figure
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