Integration of a mean-torque diesel engine model into a hardware-in-the-loop shipboard network simulation using lambda tuning

This study describes the creation of a hardware-in-the-loop (HIL) environment for use in evaluating network architecture, control concepts and equipment for use within marine electrical systems. The environment allows a scaled hardware network to be connected to a simulation of a multi-megawatt marine diesel prime mover, coupled via a synchronous generator. This allows All-Electric marine scenarios to be investigated without large-scale hardware trials. The method of closing the loop between simulation and hardware is described, with particular reference to the control of the laboratory synchronous machine, which represents the simulated generator(s). The fidelity of the HIL simulation is progressively improved in this study. First, a faster and more powerful field drive is implemented to improve voltage tracking. Second, the phase tracking is improved by using two nested proportional–integral–derivative–acceleration controllers for torque control, tuned using lambda tuning. The HIL environment is tested using a scenario involving a large constant-power load step. This provides a very severe test of the HIL environment, and also reveals the potentially adverse effects of constant-power loads within marine power systems

HardIDX: Practical and Secure Index with SGX

Software-based approaches for search over encrypted data are still either challenged by lack of proper, low-leakage encryption or slow performance. Existing hardware-based approaches do not scale well due to hardware limitations and software designs that are not specifically tailored to the hardware architecture, and are rarely well analyzed for their security (e.g., the impact of side channels). Additionally, existing hardware-based solutions often have a large code footprint in the trusted environment susceptible to software compromises. In this paper we present HardIDX: a hardware-based approach, leveraging Intel's SGX, for search over encrypted data. It implements only the security critical core, i.e., the search functionality, in the trusted environment and resorts to untrusted software for the remainder. HardIDX is deployable as a highly performant encrypted database index: it is logarithmic in the size of the index and searches are performed within a few milliseconds rather than seconds. We formally model and prove the security of our scheme showing that its leakage is equivalent to the best known searchable encryption schemes. Our implementation has a very small code and memory footprint yet still scales to virtually unlimited search index sizes, i.e., size is limited only by the general - non-secure - hardware resources

Automated Synthesis of SEU Tolerant Architectures from OO Descriptions

SEU faults are a well-known problem in aerospace environment but recently their relevance grew up also at ground level in commodity applications coupled, in this frame, with strong economic constraints in terms of costs reduction. On the other hand, latest hardware description languages and synthesis tools allow reducing the boundary between software and hardware domains making the high-level descriptions of hardware components very similar to software programs. Moving from these considerations, the present paper analyses the possibility of reusing Software Implemented Hardware Fault Tolerance (SIHFT) techniques, typically exploited in micro-processor based systems, to design SEU tolerant architectures. The main characteristics of SIHFT techniques have been examined as well as how they have to be modified to be compatible with the synthesis flow. A complete environment is provided to automate the design instrumentation using the proposed techniques, and to perform fault injection experiments both at behavioural and gate level. Preliminary results presented in this paper show the effectiveness of the approach in terms of reliability improvement and reduced design effort

The cyber security learning and research environment

This report outlines the design and configuration of the Cyber Security Learning and Research Environment (CLARE). It explains how such a system can be implemented with minimal hardware either on a single machine or across multiple machines. Moreover, details of the design of the components that constitute the environment are provided alongside sufficient implementation and configuration documentation to allow for replication of the environment

Evaluating Rapid Application Development with Python for Heterogeneous Processor-based FPGAs

As modern FPGAs evolve to include more het- erogeneous processing elements, such as ARM cores, it makes sense to consider these devices as processors first and FPGA accelerators second. As such, the conventional FPGA develop- ment environment must also adapt to support more software- like programming functionality. While high-level synthesis tools can help reduce FPGA development time, there still remains a large expertise gap in order to realize highly performing implementations. At a system-level the skill set necessary to integrate multiple custom IP hardware cores, interconnects, memory interfaces, and now heterogeneous processing elements is complex. Rather than drive FPGA development from the hardware up, we consider the impact of leveraging Python to ac- celerate application development. Python offers highly optimized libraries from an incredibly large developer community, yet is limited to the performance of the hardware system. In this work we evaluate the impact of using PYNQ, a Python development environment for application development on the Xilinx Zynq devices, the performance implications, and bottlenecks associated with it. We compare our results against existing C-based and hand-coded implementations to better understand if Python can be the glue that binds together software and hardware developers.Comment: To appear in 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM'17

Wi-PoS : a low-cost, open source ultra-wideband (UWB) hardware platform with long range sub-GHz backbone

Ultra-wideband (UWB) localization is one of the most promising approaches for indoor localization due to its accurate positioning capabilities, immunity against multipath fading, and excellent resilience against narrowband interference. However, UWB researchers are currently limited by the small amount of feasible open source hardware that is publicly available. We developed a new open source hardware platform, Wi-PoS, for precise UWB localization based on Decawave’s DW1000 UWB transceiver with several unique features: support of both long-range sub-GHz and 2.4 GHz back-end communication between nodes, flexible interfacing with external UWB antennas, and an easy implementation of the MAC layer with the Time-Annotated Instruction Set Computer (TAISC) framework. Both hardware and software are open source and all parameters of the UWB ranging can be adjusted, calibrated, and analyzed. This paper explains the main specifications of the hardware platform, illustrates design decisions, and evaluates the performance of the board in terms of range, accuracy, and energy consumption. The accuracy of the ranging system was below 10 cm in an indoor lab environment at distances up to 5 m, and accuracy smaller than 5 cm was obtained at 50 and 75 m in an outdoor environment. A theoretical model was derived for predicting the path loss and the influence of the most important ground reflection. At the same time, the average energy consumption of the hardware was very low with only 81 mA for a tag node and 63 mA for the active anchor nodes, permitting the system to run for several days on a mobile battery pack and allowing easy and fast deployment on sites without an accessible power supply or backbone network. The UWB hardware platform demonstrated flexibility, easy installation, and low power consumption

Diagnosing faults in autonomous robot plan execution

A major requirement for an autonomous robot is the capability to diagnose faults during plan execution in an uncertain environment. Many diagnostic researches concentrate only on hardware failures within an autonomous robot. Taking a different approach, the implementation of a Telerobot Diagnostic System that addresses, in addition to the hardware failures, failures caused by unexpected event changes in the environment or failures due to plan errors, is described. One feature of the system is the utilization of task-plan knowledge and context information to deduce fault symptoms. This forward deduction provides valuable information on past activities and the current expectations of a robotic event, both of which can guide the plan-execution inference process. The inference process adopts a model-based technique to recreate the plan-execution process and to confirm fault-source hypotheses. This technique allows the system to diagnose multiple faults due to either unexpected plan failures or hardware errors. This research initiates a major effort to investigate relationships between hardware faults and plan errors, relationships which were not addressed in the past. The results of this research will provide a clear understanding of how to generate a better task planner for an autonomous robot and how to recover the robot from faults in a critical environment