ASIC Technology Migrations: A Design Guide for First Pass Success

This thesis presents a study of Application Specific Integrated Circuit (ASIC) technology migrations. An overview of the design flow methodology used for completing a ASIC design from concept to silicon is presented. The design flow is then augmented with special considerations specifically for ASIC technology migrations. An ASIC technology migration design example, using the special considerations, is preseted. Finally, a summary is presented with considerations regarding future work

Hardware Architecture Study for NASA's Space Software Defined Radios

This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios

Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 2: Army fault tolerant architecture design and analysis

Described here is the Army Fault Tolerant Architecture (AFTA) hardware architecture and components and the operating system. The architectural and operational theory of the AFTA Fault Tolerant Data Bus is discussed. The test and maintenance strategy developed for use in fielded AFTA installations is presented. An approach to be used in reducing the probability of AFTA failure due to common mode faults is described. Analytical models for AFTA performance, reliability, availability, life cycle cost, weight, power, and volume are developed. An approach is presented for using VHSIC Hardware Description Language (VHDL) to describe and design AFTA's developmental hardware. A plan is described for verifying and validating key AFTA concepts during the Dem/Val phase. Analytical models and partial mission requirements are used to generate AFTA configurations for the TF/TA/NOE and Ground Vehicle missions

Spectrum sensing through software defined radio

Dissertação apresentada para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores, pela Universidade Nova de Lisboa, Faculdade de Ciências e TecnologiaA change in paradigm when it comes to controlling radio transmissions is in course. Tasks usually executed in an exclusive class of hardware systems are increasingly controlled by software systems. A deep change to the software domain is foreseeable, creating a true Software Defined Radio. At the same time this change occurs, the radioelectric spectrum is almost completely licensed. However, the spectrum is rarely used to its full extent over time, enabling its opportunistic use while the licensed devices do not communicate. This is a part of the notion of Cognitive Radio, a new kind of radio capable of using the spectrum in an opportunistic way. These two new paradigms in radio access can be combined to produce a exible and reliable radio, overcoming the issues with radioelectric spectrum scarcity. This dissertation starts an exploration in this area by combining these two paradigms through the use of an Energy Detector implemented in a Universal Software Radio Peripheral device and using the GNURadio suite. The performance of such a system is tested by calculating the Probabilities of Detection and False Alarm in real scenarios and comparing them to the expected theoretical values. A method for defining thresholds for narrowband signals is also tested based on works in Information Theory concepts, i.e.,the Akaike Information Criteria and the Minimum Description Length. The results are tested for a real transmission using two USRP platforms communicating with each other,one acting as the licensed user and the other acting as the secondary, opportunistic user. Finally, we highlight the technological work developed in this dissertation, which may support future research works through the use of the developed scripts, allowing a faster method to test algorithms with different parameterization

Belle II Technical Design Report

The Belle detector at the KEKB electron-positron collider has collected almost 1 billion Y(4S) events in its decade of operation. Super-KEKB, an upgrade of KEKB is under construction, to increase the luminosity by two orders of magnitude during a three-year shutdown, with an ultimate goal of 8E35 /cm^2 /s luminosity. To exploit the increased luminosity, an upgrade of the Belle detector has been proposed. A new international collaboration Belle-II, is being formed. The Technical Design Report presents physics motivation, basic methods of the accelerator upgrade, as well as key improvements of the detector.Comment: Edited by: Z. Dole\v{z}al and S. Un

The GENCOD project : Automated generation of Hardware code for safety critical applications on FPGA targets

International audienceGENCOD is a research project for solutions to automated generation of safe code for Field Programmable Gate Arrays (FPGA) targets. The paper will describe typical ASIC/FPGA workflow, and current implementation for airborne electronic hardware design. Major stakes in certification for airborne electronic hardware will be discussed. The next part will detail the project, the proposed workflow and the associated tools. We will present the current experimentations. Finally, the conclusion will expose advantages and drawbacks of such approach

High-level synthesis for FPGAs: From prototyping to deployment

Abstract-Escalating System-on-Chip design complexity is pushing the design community to raise the level of abstraction beyond RTL. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS methodology is happening now, especially for FPGA designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. Index Terms-Domain-specific design, field-programmable gate array (FPGA), high-level synthesis (HLS), quality of results (QoR)