The NASA SBIR product catalog

The purpose of this catalog is to assist small business firms in making the community aware of products emerging from their efforts in the Small Business Innovation Research (SBIR) program. It contains descriptions of some products that have advanced into Phase 3 and others that are identified as prospective products. Both lists of products in this catalog are based on information supplied by NASA SBIR contractors in responding to an invitation to be represented in this document. Generally, all products suggested by the small firms were included in order to meet the goals of information exchange for SBIR results. Of the 444 SBIR contractors NASA queried, 137 provided information on 219 products. The catalog presents the product information in the technology areas listed in the table of contents. Within each area, the products are listed in alphabetical order by product name and are given identifying numbers. Also included is an alphabetical listing of the companies that have products described. This listing cross-references the product list and provides information on the business activity of each firm. In addition, there are three indexes: one a list of firms by states, one that lists the products according to NASA Centers that managed the SBIR projects, and one that lists the products by the relevant Technical Topics utilized in NASA's annual program solicitation under which each SBIR project was selected

Rosina - Rosetta Orbiter Spectrometer for Ion and Neutral Analysis

The Rosetta Orbiter Spectrometer for Ion and Neutral Analysis (ROSINA) will answer important questions posed by the mission's main objectives. After Giotto, this will be the first time the volatile part of a comet will be analyzed in situ. This is a very important investigation, as comets, in contrast to meteorites, have maintained most of the volatiles of the solar nebula. To accomplish the very demanding objectives through all the different phases of the comet's activity, ROSINA has unprecedented capabilities including very wide mass range (1 to >300 amu), very high mass resolution (m/Δ m > 3000, i.e. the ability to resolve CO from N2 and 13C from 12CH), very wide dynamic range and high sensitivity, as well as the ability to determine cometary gas velocities, and temperature. ROSINA consists of two mass spectrometers for neutrals and primary ions with complementary capabilities and a pressure sensor. To ensure that absolute gas densities can be determined, each mass spectrometer carries a reservoir of a calibrated gas mixture allowing in-flight calibration. Furthermore, identical flight-spares of all three sensors will serve for detailed analysis of all relevant parameters, in particular the sensitivities for complex organic molecules and their fragmentation patterns in our electron bombardment ion source

Built-In Self-Test Quality Assessment Using Hardware Fault Emulation in FPGAs

This paper addresses the problem of test quality assessment, namely of BIST solutions, implemented in FPGA and/or in ASIC, through Hardware Fault Emulation (HFE). A novel HFE methodology and tool is proposed, that, using partial reconfiguration, efficiently measures the quality of the BIST solution. The proposed HFE methodology uses Look-Up Tables (LUTs) fault models and is performed using local partial reconfiguration for fault injection on Xilinx(TM) Virtex and/or Spartan FPGA components, with small binary files. For ASIC cores, HFE is used to validate test vector selection to achieve high fault coverage on the physical structure. The methodology is fully automated. Results on ISCAS benchmarks and on an ARM core show that HFE can be orders of magnitude faster than software fault simulation or fully reconfigurable hardware fault emulation

Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters

High Performance and Energy Efficiency are critical requirements for Internet of Things (IoT) end-nodes. Exploiting tightly-coupled clusters of programmable processors (CMPs) has recently emerged as a suitable solution to address this challenge. One of the main bottlenecks limiting the performance and energy efficiency of these systems is the instruction cache architecture due to its criticality in terms of timing (i.e., maximum operating frequency), bandwidth, and power. We propose a hierarchical instruction cache tailored to ultra-low-power tightly-coupled processor clusters where a relatively large cache (L1.5) is shared by L1 private caches through a two-cycle latency interconnect. To address the performance loss caused by the L1 capacity misses, we introduce a next-line prefetcher with cache probe filtering (CPF) from L1 to L1.5. We optimize the core instruction fetch (IF) stage by removing the critical core-to-L1 combinational path. We present a detailed comparison of instruction cache architectures' performance and energy efficiency for parallel ultra-low-power (ULP) clusters. Focusing on the implementation, our two-level instruction cache provides better scalability than existing shared caches, delivering up to 20\% higher operating frequency. On average, the proposed two-level cache improves maximum performance by up to 17\% compared to the state-of-the-art while delivering similar energy efficiency for most relevant applications.Comment: 14 page

Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters

High performance and energy efficiency are critical requirements for Internet of Things (IoT) end-nodes. Exploiting tightly coupled clusters of programmable processors (CMPs) has recently emerged as a suitable solution to address this challenge. One of the main bottlenecks limiting the performance and energy efficiency of these systems is the instruction cache architecture due to its criticality in terms of timing (i.e., maximum operating frequency), bandwidth, and power. We propose a hierarchical instruction cache tailored to ultralow-power (ULP) tightly coupled processor clusters where a relatively large cache (L1.5) is shared by L1 private (PR) caches through a two-cycle latency interconnect. To address the performance loss caused by the L1 capacity misses, we introduce a next-line prefetcher with cache probe filtering (CPF) from L1 to L1.5. We optimize the core instruction fetch (IF) stage by removing the critical core-to-L1 combinational path. We present a detailed comparison of instruction cache architectures' performance and energy efficiency for parallel ULP (PULP) clusters. Focusing on the implementation, our two-level instruction cache provides better scalability than existing shared caches, delivering up to 20% higher operating frequency. On average, the proposed two-level cache improves maximum performance by up to 17% compared to the state-of-the-art while delivering similar energy efficiency for most relevant applications

NASA SBIR product catalog, 1991

This catalog is a partial list of products of NASA SBIR (Small Business Innovation Research) projects that have advanced to some degree into Phase 3. While most of the products evolved from work conducted during SBIR Phase 1 and 2, a few advanced to commercial status solely from Phase 1 activities. The catalog presents information provided to NASA by SBIR contractors who wished to have their products exhibited at Technology 2001, a NASA-sponsored technology transfer conference held in San Jose, California, on December 4, 5, and 6, 1991. The catalog presents the product information in the following technology areas: computer and communication systems; information processing and AI; robotics and automation; signal and image processing; microelectronics; electronic devices and equipment; microwave electronic devices; optical devices and lasers; advanced materials; materials processing; materials testing and NDE; materials instrumentation; aerodynamics and aircraft; fluid mechanics and measurement; heat transfer devices; refrigeration and cryogenics; energy conversion devices; oceanographic instruments; atmosphere monitoring devices; water management; life science instruments; and spacecraft electromechanical systems

Design and Evaluation of a Single Phase 5 Level Full Bridge Neutral Point Clamped Multi Level Converter

This thesis describes multilevel converters (MLC) designed for use with a repurposed electronic vehicle battery (battery 2nd life). MLC is of particular interest due to the low harmonic distortion content and reduced voltage stress in the switching devices. A detailed study of the MLC topologies and modulation techniques is presented. Space vector modulation is analysed and implemented to evaluate the converter. A comprehensive assessment of the MLC is presented using wide bandgap (WBG) devices highlighting the devices’ thermal and high switching frequency features

Autonomous Mechanical Assembly on the Space Shuttle: An Overview

The space shuttle will be equipped with a pair of 50 ft. manipulators used to handle payloads and to perform mechanical assembly operations. Although current plans call for these manipulators to be operated by a human teleoperator. The possibility of using results from robotics and machine intelligence to automate this shuttle assembly system was investigated. The major components of an autonomous mechanical assembly system are examined, along with the technology base upon which they depend. The state of the art in advanced automation is also assessed