Design Space Exploration for Building Automation Systems

In the building automation domain, there are gaps among various tasks related to design engineering. As a result created system designs must be adapted to the given requirements on system functionality, which is related to increased costs and engineering effort than planned. For this reason standards are prepared to enable a coordination among these tasks by providing guidelines and unified artifacts for the design. Moreover, a huge variety of prefabricated devices offered from different manufacturers on the market for building automation that realize building automation functions by preprogrammed software components. Current methods for design creation do not consider this variety and design solution is limited to product lines of a few manufacturers and expertise of system integrators. Correspondingly, this results in design solutions of a limited quality. Thus, a great optimization potential of the quality of design solutions and coordination of tasks related to design engineering arises. For given design requirements, the existence of a high number of devices that realize required functions leads to a combinatorial explosion of design alternatives at different price and quality levels. Finding optimal design alternatives is a hard problem to which a new solution method is proposed based on heuristical approaches. By integrating problem specific knowledge into algorithms based on heuristics, a promisingly high optimization performance is achieved. Further, optimization algorithms are conceived to consider a set of flexibly defined quality criteria specified by users and achieve system design solutions of high quality. In order to realize this idea, optimization algorithms are proposed in this thesis based on goal-oriented operations that achieve a balanced convergence and exploration behavior for a search in the design space applied in different strategies. Further, a component model is proposed that enables a seamless integration of design engineering tasks according to the related standards and application of optimization algorithms.:1 Introduction 17 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3 Goals and Use of the Thesis . . . . . . . . . . . . . . . . . . . . . 21 1.4 Solution Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . 24 2 Design Creation for Building Automation Systems 25 2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 Engineering of Building Automation Systems . . . . . . . . . . . 29 2.3 Network Protocols of Building Automation Systems . . . . . . . 33 2.4 Existing Solutions for Design Creation . . . . . . . . . . . . . . . 34 2.5 The Device Interoperability Problem . . . . . . . . . . . . . . . . 37 2.6 Guidelines for Planning of Room Automation Systems . . . . . . 38 2.7 Quality Requirements on BAS . . . . . . . . . . . . . . . . . . . 41 2.8 Quality Requirements on Design . . . . . . . . . . . . . . . . . . 42 2.8.1 Quality Requirements Related to Project Planning . . . . 42 2.8.2 Quality Requirements Related to Project Implementation 43 2.9 Quality Requirements on Methods . . . . . . . . . . . . . . . . . 44 2.10 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3 The Design Creation Task 47 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2 System Design Composition Model . . . . . . . . . . . . . . . . . 49 3.2.1 Abstract and Detailed Design Model . . . . . . . . . . . . 49 3.2.2 Mapping Model . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3 Formulation of the Problem . . . . . . . . . . . . . . . . . . . . . 53 3.3.1 Problem properties . . . . . . . . . . . . . . . . . . . . . . 54 3.3.2 Requirements on Algorithms . . . . . . . . . . . . . . . . 56 3.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4 Solution Methods for Design Generation and Optimization 59 4.1 Combinatorial Optimization . . . . . . . . . . . . . . . . . . . . . 59 4.2 Metaheuristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3 Examples for Metaheuristics . . . . . . . . . . . . . . . . . . . . . 62 4.3.1 Simulated Annealing . . . . . . . . . . . . . . . . . . . . . 62 4.3.2 Tabu Search . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.3 Ant Colony Optimization . . . . . . . . . . . . . . . . . . 65 4.3.4 Evolutionary Computation . . . . . . . . . . . . . . . . . 66 4.4 Choice of the Solver Algorithm . . . . . . . . . . . . . . . . . . . 69 4.5 Specialized Methods for Diversity Preservation . . . . . . . . . . 70 4.6 Approaches for Real World Problems . . . . . . . . . . . . . . . . 71 4.6.1 Component-Based Mapping Problems . . . . . . . . . . . 71 4.6.2 Network Design Problems . . . . . . . . . . . . . . . . . . 73 4.6.3 Comparison of Solution Methods . . . . . . . . . . . . . . 74 4.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5 Automated Creation of Optimized Designs 79 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2 Design Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3 Component Model . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.3.1 Presumptions . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.2 Integration of Component Model . . . . . . . . . . . . . . 87 5.4 Design Generation . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.4.1 Component Search . . . . . . . . . . . . . . . . . . . . . . 88 5.4.2 Generation Approaches . . . . . . . . . . . . . . . . . . . 100 5.5 Design Improvement . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.5.1 Problems and Requirements . . . . . . . . . . . . . . . . . 107 5.5.2 Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.5.3 Application Strategies . . . . . . . . . . . . . . . . . . . . 121 5.6 Realization of the Approach . . . . . . . . . . . . . . . . . . . . . 122 5.6.1 Objective Functions . . . . . . . . . . . . . . . . . . . . . 122 5.6.2 Individual Representation . . . . . . . . . . . . . . . . . . 123 5.7 Automated Design Creation For A Building . . . . . . . . . . . . 124 5.7.1 Room Spanning Control . . . . . . . . . . . . . . . . . . . 124 5.7.2 Flexible Rooms . . . . . . . . . . . . . . . . . . . . . . . . 125 5.7.3 Technology Spanning Designs . . . . . . . . . . . . . . . . 129 5.7.4 Preferences for Mapping of Function Blocks to Devices . . 132 5.8 Further Uses and Applicability of the Approach . . . . . . . . . . 133 5.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6 Validation and Performance Analysis 137 6.1 Validation Method . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.2 Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.3 Example Abstract Designs and Performance Tests . . . . . . . . 139 6.3.1 Criteria for Choosing Example Abstract Designs . . . . . 139 6.3.2 Example Abstract Designs . . . . . . . . . . . . . . . . . . 140 6.3.3 Performance Tests . . . . . . . . . . . . . . . . . . . . . . 142 6.3.4 Population Size P - Analysis . . . . . . . . . . . . . . . . 151 6.3.5 Cross-Over Probability pC - Analysis . . . . . . . . . . . 157 6.3.6 Mutation Probability pM - Analysis . . . . . . . . . . . . 162 6.3.7 Discussion for Optimization Results and Example Designs 168 6.3.8 Resource Consumption . . . . . . . . . . . . . . . . . . . . 171 6.3.9 Parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6.4 Optimization Framework . . . . . . . . . . . . . . . . . . . . . . . 172 6.5 Framework Design . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.5.1 Components and Interfaces . . . . . . . . . . . . . . . . . 174 6.5.2 Workflow Model . . . . . . . . . . . . . . . . . . . . . . . 177 6.5.3 Optimization Control By Graphical User Interface . . . . 180 6.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 7 Conclusions 185 A Appendix of Designs 189 Bibliography 201 Index 21

WIMAX LINK PERFORMANCE ANALYSIS FOR WIRELESS AUTOMATION APPLICATIONS

Wireless broadband access technologies are rapidly growing and a corresponding growth in the demand of its applicability transcends faster internet access, high speed file download and different multimedia applications such as voice calls, video streaming, teleconferencing etc, to industrial operations and automation. Industrial and automation systems perform operations that requires the transmission of real time information from one end to another through high-performance wireless broadband communication links. WiMAX, based on IEEE 802.16 standard is one of the wireless broadband access technologies that has overcome location, speed, and access limitations of the traditional Digital Subscriber Line and Wireless Fidelity, and offers high efficient data rates. This thesis presents detailed analysis of operational WiMAX link performance parameters such as throughput, latency, jitter, and packet loss for suitable applicability in wireless automation applications. The theoretical background of components and functionalities of WiMAX physical and MAC layers as well as the network performance features are presented. The equipment deployed for this field experiment are Alvarion BreeZeMAX 3000 fixed WiMAX equipment operating in the 3.5 GHz licensed band with channel bandwidth of 3.5 MHz. The deployed equipment consisting of MBSE and CPE are installed and commissioned prior to field tests. Several measurements are made in three link quality scenarios (sufficient, good and excellent) in the University of Vaasa campus. Observations and results obtained are discussed and analyzed.fi=Opinnäytetyö kokotekstinä PDF-muodossa.|en=Thesis fulltext in PDF format.|sv=Lärdomsprov tillgängligt som fulltext i PDF-format

Enabling Tetherless Care with Context-Awareness and Opportunistic Communication

Tetherless care is a novel healthcare delivery paradigm that enables an interaction between caregivers and patients beyond the confines of traditional points of care. This thesis presents a synthesis of recent advances in wearable, ubiquitous sensing; mobile computing; wireless networks; and health information technology into a cohesive framework that enables and supports the tetherless care concept. Tetherless care is formally defined and modeled in a higher order logical framework. The model distills three relations between several classes in the model's domain of discourse. A prototype implementation is developed and evaluated to capture and represent the logical classes of tetherless care and provide the development infrastructure upon which the relational logic outlined by the model can be implemented. An algorithm is presented and evaluated to support the delivery of traffic between mobile devices and servers despite intermittent connectivity given the changing urgency of the patient's situation. And an example tetherless care application is presented, developed for the framework, and compared with its deployment on a similar platform. Results show that contemporary mobile devices supply sufficient power to support 24 hours of operation and that, at least, some patient environments provide sufficient opportunities for connectivity to reliably meet the demands of some tetherless care applications, ultimately leading to a conclusion of proof-of-concept for tetherless care

Harzer Roller: Linker-Based Instrumentation for Enhanced Embedded Security Testing

Due to the rise of the Internet of Things, there are many new chips and platforms available for hobbyists and industry alike to build smart devices. The SDKs for these new platforms usually include closed-source binaries containing wireless protocol implementations, cryptographic implementations, or other library functions, which are shared among all user code across the platform. Leveraging such a library vulnerability has a high impact on a given platform. However, as these platforms are often shipped ready-to-use, classic debug infrastructure like JTAG is often times not available. In this paper, we present a method, called Harzer Roller, to enhance embedded firmware security testing on resource-constrained devices. With the Harzer Roller, we hook instrumentation code into function call and return. The hooking not only applies to the user application code but to the SDK used to build firmware as well. While we keep the design of the Harzer Rollergenerally architecture independent, we provide an implementation for the ESP8266 Wi-Fi IoT chip based on the xtensa architecture. We show that the Harzer Roller can be leveraged to trace execution flow through libraries without available source code and to detect stack-based buffer-overflows. Additionally, we showcase how the overflow detection can be used to dump debugging information for later analysis. This enables better usage of a variety of software security testing methods like fuzzing of wireless protocol implementations or proof-of-concept attack development.Comment: 9 Pages, 7 Figures, ROOTS'1

Energy-Efficient Fault-Tolerant Scheduling Algorithm for Real-Time Tasks in Cloud-Based 5G Networks

© 2013 IEEE. Green computing has become a hot issue for both academia and industry. The fifth-generation (5G) mobile networks put forward a high request for energy efficiency and low latency. The cloud radio access network provides efficient resource use, high performance, and high availability for 5G systems. However, hardware and software faults of cloud systems may lead to failure in providing real-time services. Developing fault tolerance technique can efficiently enhance the reliability and availability of real-time cloud services. The core idea of fault-tolerant scheduling algorithm is introducing redundancy to ensure that the tasks can be finished in the case of permanent or transient system failure. Nevertheless, the redundancy incurs extra overhead for cloud systems, which results in considerable energy consumption. In this paper, we focus on the problem of how to reduce the energy consumption when providing fault tolerance. We first propose a novel primary-backup-based fault-tolerant scheduling architecture for real-time tasks in the cloud environment. Based on the architecture, we present an energy-efficient fault-tolerant scheduling algorithm for real-time tasks (EFTR). EFTR adopts a proactive strategy to increase the system processing capacity and employs a rearrangement mechanism to improve the resource utilization. Simulation experiments are conducted on the CloudSim platform to evaluate the feasibility and effectiveness of EFTR. Compared with the existing fault-tolerant scheduling algorithms, EFTR shows excellent performance in energy conservation and task schedulability

Fast Memory-Based Processing in Software-Defined Radios

Negli ultimi anni le Software Defined Radio sono state un argomento di ricerca di primo piano nell'ambito dei sistemi di trasmissione radio. Molti e variegati paradigmi implementativi sono stati concepiti e proposti, con soluzioni capaci di spaziare da sistemi basati su Field Programmable Gate Array (FPGA) a implementazioni ottenute mediante un singolo General Purpose Processor (GPP) passando per dispositivi caratterizzati dalla presenza computazionalmente preponderante di un Digital Signal Processor (DSP) o da architetture miste. Tali soluzioni rappresentano punti di equilibrio diversi dell'inevitabile compromesso tra flessibilità e capacità computazionale del sistema di trasmissione implementato, comprimendo in qualche modo l'aspirazione ad un sistema radio universale propria del concetto originario dell'SDR. A questo riguardo, le soluzioni SDR basate su GPP rappresentano il modello implementativo maggiormente desiderabile in quanto costituiscono l'alternativa più flessibile ed economica tra tutte le tipologie di SDR. Ciò nonostante, la scarsa capacità computazionale ha sempre limitato l'adozione di questi sistemi in scenari produttivi di vasta scala. Se convenientemente applicati entro il contesto di sviluppo SDR, concetti classici noti in informatica sotto la denominazione collettiva di space/time trade-off possono essere di enorme aiuto quando si cerchi di mitigare un simile problema. Traendo ispirazione da detti concetti, nonché estendendoli ed applicandoli all'abito dell'SDR, questa tesi sviluppa e presenta una tecnica di programmazione specifica per software radio chiamata Memory Acceleration (MA) che, mediante un uso estensivo delle risorse di memoria disponibili a bordo di un tipico sistema di calcolo general purpose, può fornire alle SDR convenzionali basate su GPP fattori di accelerazione sostanziali (circa un ordine di grandezza) senza ridurne la peculiare flessibilità. Alcune rilevanti implementazioni di sistemi SDR capaci di lavorare in tempo reale su processori GPP consumer-grade realizzate in tecnica MA sono descritte in dettaglio entro questo lavoro di tesi e fornite come prova della reale efficacia del concetto proposto

Energy-efficient design and implementation of turbo codes for wireless sensor network

The objective of this thesis is to apply near Shannon limit Error-Correcting Codes (ECCs), particularly the turbo-like codes, to energy-constrained wireless devices, for the purpose of extending their lifetime. Conventionally, sophisticated ECCs are applied to applications, such as mobile telephone networks or satellite television networks, to facilitate long range and high throughput wireless communication. For low power applications, such as Wireless Sensor Networks (WSNs), these ECCs were considered due to their high decoder complexities. In particular, the energy efficiency of the sensor nodes in WSNs is one of the most important factors in their design. The processing energy consumption required by high complexity ECCs decoders is a significant drawback, which impacts upon the overall energy consumption of the system. However, as Integrated Circuit (IC) processing technology is scaled down, the processing energy consumed by hardware resources reduces exponentially. As a result, near Shannon limit ECCs have recently begun to be considered for use in WSNs to reduce the transmission energy consumption [1,2]. However, to ensure that the transmission energy consumption reduction granted by the employed ECC makes a positive improvement on the overall energy efficiency of the system, the processing energy consumption must still be carefully considered.The main subject of this thesis is to optimise the design of turbo codes at both an algorithmic and a hardware implementation level for WSN scenarios. The communication requirements of the target WSN applications, such as communication distance, channel throughput, network scale, transmission frequency, network topology, etc, are investigated. Those requirements are important factors for designing a channel coding system. Especially when energy resources are limited, the trade-off between the requirements placed on different parameters must be carefully considered, in order to minimise the overall energy consumption. Moreover, based on this investigation, the advantages of employing near Shannon limit ECCs in WSNs are discussed. Low complexity and energy-efficient hardware implementations of the ECC decoders are essential for the target applications

Programming techniques for efficient and interoperable software defined radios

Recently, Software-Dened Radios (SDRs) has became a hot research topic in wireless communications eld. This is jointly due to the increasing request of reconfigurable and interoperable multi-standard radio systems able to learn from their surrounding environment and efficiently exploit the available frequency spectrum resources, so realizing the cognitive radio paradigm, and to the availability of reprogrammable hardware architectures providing the computing power necessary to meet the tight real-time constraints typical of the state-of-art wideband communications standards. Most SDR implementations are based on mixed architectures in which Field Programmable Gate Arrays (FPGA), Digital Signal Processors (DSP) and General Purpose Processors (GPP) coexist. GPP-based solutions, even if providing the highest level of flexibility, are typically avoided because of their computational inefficiency and power consumption. Starting from these assumptions, this thesis tries to jointly face two of the main important issues in GPP-based SDR systems: the computational efficiency and the interoperability capacity. In the first part, this thesis presents the potential of a novel programming technique, named Memory Acceleration (MA), in which the memory resources typical of GPP-based systems are used to assist central processor in executing real-time signal processing operations. This technique, belonging to the classical computer-science optimization techniques known as Space-Time trade-offs, defines novel algorithmic methods to assist developers in designing their software-defined signal processing algorithms. In order to show its applicability some "real-world" case studies are presented together with the acceleration factor obtained. In the second part of the thesis, the interoperability issue in SDR systems is also considered. Existing software architectures, like the Software Communications Architecture (SCA), abstract the hardware/software components of a radio communications chain using a middleware like CORBA for providing full portability and interoperability to the implemented chain, called waveform in the SCA parlance. This feature is paid in terms of computational overhead introduced by the software communications middleware and this is one of the reasons why GPP-based architecture are generally discarded also for the implementation of narrow-band SCA-compliant communications standards. In this thesis we briefly analyse SCA architecture and an open-source SCA-compliant framework, ie. OSSIE, and provide guidelines to enable component-based multithreading programming and CPU affinity in that framework. We also detail the implementation of a real-time SCA-compliant waveform developed inside this modified framework, i.e. the VHF analogue aeronautical communications transceiver. Finally, we provide the proof of how it is possible to implement an efficient and interoperable real-time wideband SCA-compliant waveform, i.e. the AeroMACS waveform, on a GPP-based architecture by merging the acceleration factor provided by MA technique and the interoperability feature ensured by SCA architecture