178 research outputs found

    Efficient parallel processing with optical interconnections

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    With the advances in VLSI technology, it is now possible to build chips which can each contain thousands of processors. The efficiency of such chips in executing parallel algorithms heavily depends on the interconnection topology of the processors. It is not possible to build a fully interconnected network of processors with constant fan-in/fan-out using electrical interconnections. Free space optics is a remedy to this limitation. Qualities exclusive to the optical medium are its ability to be directed for propagation in free space and the property that optical channels can cross in space without any interference. In this thesis, we present an electro-optical interconnected architecture named Optical Reconfigurable Mesh (ORM). It is based on an existing optical model of computation. There are two layers in the architecture. The processing layer is a reconfigurable mesh and the deflecting layer contains optical devices to deflect light beams. ORM provides three types of communication mechanisms. The first is for arbitrary planar connections among sets of locally connected processors using the reconfigurable mesh. The second is for arbitrary connections among N of the processors using the electrical buses on the processing layer and N2 fixed passive deflecting units on the deflection layer. The third is for arbitrary connections among any of the N2 processors using the N2 mechanically reconfigurable deflectors in the deflection layer. The third type of communication mechanisms is significantly slower than the other two. Therefore, it is desirable to avoid reconfiguring this type of communication during the execution of the algorithms. Instead, the optical reconfiguration can be done before the execution of each algorithm begins. Determining a right configuration that would be suitable for the entire configuration of a task execution is studied in this thesis. The basic data movements for each of the mechanisms are studied. Finally, to show the power of ORM, we use all three types of communication mechanisms in the first O(logN) time algorithm for finding the convex hulls of all figures in an N x N binary image presented in this thesis

    NASA Tech Briefs, April 2003

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    Topics include: Tool for Bending a Metal Tube Precisely in a Confined Space; Multiple-Use Mechanisms for Attachment to Seat Tracks; Force-Measuring Clamps; Cellular Pressure-Actuated Joint; Block QCA Fault-Tolerant Logic Gates; Hybrid VLSI/QCA Architecture for Computing FFTs; Arrays of Carbon Nanotubes as RF Filters in Waveguides; Carbon Nanotubes as Resonators for RF Spectrum Analyzers; Software for Viewing Landsat Mosaic Images; Updated Integrated Mission Program; Software for Sharing and Management of Information; Optical-Quality Thin Polymer Membranes; Rollable Thin Shell Composite-Material Paraboloidal Mirrors; Folded Resonant Horns for Power Ultrasonic Applications; Touchdown Ball-Bearing System for Magnetic Bearings; Flux-Based Deadbeat Control of Induction-Motor Torque; Block Copolymers as Templates for Arrays of Carbon Nanotubes; Throttling Cryogen Boiloff To Control Cryostat Temperature; Collaborative Software Development Approach Used to Deliver the New Shuttle Telemetry Ground Station; Turbulence in Supercritical O2/H2 and C7H16/N2 Mixing Layers; and Time-Resolved Measurements in Optoelectronic Microbioanal

    Progress in the Smart Pixel Technologies

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    The purpose of this paper is to review the recent progress in the developing smart pixel technologies. The paper begins by reviewing some of the rapidly evolving smart pixel terminologies. It then describes several of the smart pixel technologies that have recently emerged. Finally, it outlines the performance of these technologies in both device complexity and aggregate capacity. The reviewed SPA technologies include both the modulator-based FET-SEED, hybrid CMOS-SEED, and LCOS smart pixels and the source-based hybrid VCSEL/MSM, ELO, flip-chip-bonded VCSEL/MSM, and monolithic MSM/MESFET/VCSEL smart pixels

    Devices and networks for optical switching

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    This thesis is concerned with some aspects of the application of optics to switching and computing. Two areas are dealt with: the design of switching networks which use optical interconnects, and the development and application of the t-SEED optical logic device. The work on optical interconnects looks at the multistage interconnection network which has been proposed as a hybrid switch using both electronics and optics. It is shown that the architecture can be mapped from one dimensional to two dimensional format, so that the machine makes full use of the space available to the optics. Other mapping rules are described which allow the network to make optimum use of the optical interconnects, and the endpoint is a hybrid optical-electronic machine which should be able to outperform an all-electronic equivalent. The development of the t-SEED optical logic device is described, which is the integration of a phototransistor with a multiple quantum well optical modulator. It is found to be important to have the modulator underneath rather than on top of the transistor to avoid unwanted thyristor action. In order for the transistor to have a high gain the collector must have a low doping level, the exit window in the substrate must be etched all the way to the emitter layer, and the etch must not damage the emitter-base junction. A real optical gain of 1.6 has been obtained, which is higher than has ever been reached before but is not as high as should be possible. Improvements to the device are suggested. A new model of the Fabry-Perot cavity is introduced which helps considerably in the interpretation of experimental measurements made on the quantum well modulators. Also a method of improving the contrast of the multiple quantum well modulator by grading the well widths is proposed which may find application in long wavelength transmission modulators. Some systems which make use of the t-SEED are considered. It is shown that the t-SEED device has the right characteristics for use as a neuron element in the optical implementation of a neural network. A new image processing network for clutter removal in binary images is introduced which uses the t-SEED, and a brief performance analysis suggests that the network may be superior to an all-electronic machine

    Sublogarithmic deterministic selection on arrays with a reconfigurable optical bus

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    The linear array with a reconfigurable pipelined bus system (LARPBS) is a newly introduced parallel computational model, where processors are connected by a reconfigurable optical bus. In this paper, we show that the selection problem can be solved on the LARPBS model deterministically in O((loglogN)2/ log log log N) time. To our best knowledge, this is the best deterministic selection algorithm on any model with a reconfigurable optical bus.Yijie Han, Yi Pan and Hong She

    Holographic optical interconnects in dichromated gelatin

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    Abstract unavailable please refer to PD

    A serial bus architecture for parallel processing systems.

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    One of the most serious deterrants to the development of multiple processor architectures has been the problem of providing adequate communication between the discrete processing elements. This paper examines two communications-based constraints. The first constraint is related to the physical structure of the VLSI chip. The wider the communication path the more pins are needed to effect the data transfer. As Integrated Circuits grow in computational power, more communication capacity is needed, pushing designs closer to the pin limitations of the packaging technology. The second constraint, somewhat related to the first, is the limited speed with which data can be transmitted via internal channels. Typical speeds one can achieve on a single wire are on the order of 1 Gbps. The recent development of an Optoelectronic Multiplexer may allow VLSI chips to communicate at rates up to 7 Gbps. An architecture for a parallel processing computer which takes advantage of this new capability is presented. The feasibility of a single-chip parallel-processor based on the Optoelectronic Multiplexer is examined by projecting current trends in processor speed, power, and transistor count into estimates of throughput for a multi-processor IC.http://hdl.handle.net/10945/22094http://archive.org/details/serialbusarchite00delaLieutenant, United States NavyApproved for public release; distribution is unlimited

    Efficient structural outlooks for vertex product networks

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    In this thesis, a new classification for a large set of interconnection networks, referred to as "Vertex Product Networks" (VPN), is provided and a number of related issues are discussed including the design and evaluation of efficient structural outlooks for algorithm development on this class of networks. The importance of studying the VPN can be attributed to the following two main reasons: first an unlimited number of new networks can be defined under the umbrella of the VPN, and second some known networks can be studied and analysed more deeply. Examples of the VPN include the newly proposed arrangement-star and the existing Optical Transpose Interconnection Systems (OTIS-networks). Over the past two decades many interconnection networks have been proposed in the literature, including the star, hyperstar, hypercube, arrangement, and OTIS-networks. Most existing research on these networks has focused on analysing their topological properties. Consequently, there has been relatively little work devoted to designing efficient parallel algorithms for important parallel applications. In an attempt to fill this gap, this research aims to propose efficient structural outlooks for algorithm development. These structural outlooks are based on grid and pipeline views as popular structures that support a vast body of applications that are encountered in many areas of science and engineering, including matrix computation, divide-and- conquer type of algorithms, sorting, and Fourier transforms. The proposed structural outlooks are applied to the VPN, notably the arrangement-star and OTIS-networks. In this research, we argue that the proposed arrangement-star is a viable candidate as an underlying topology for future high-speed parallel computers. Not only does the arrangement-star bring a solution to the scalability limitations from which the Abstract existing star graph suffers, but it also enables the development of parallel algorithms based on the proposed structural outlooks, such as matrix computation, linear algebra, divide-and-conquer algorithms, sorting, and Fourier transforms. Results from a performance study conducted in this thesis reveal that the proposed arrangement-star supports efficiently applications based on the grid or pipeline structural outlooks. OTIS-networks are another example of the VPN. This type of networks has the important advantage of combining both optical and electronic interconnect technology. A number of studies have recently explored the topological properties of OTIS-networks. Although there has been some work on designing parallel algorithms for image processing and sorting, hardly any work has considered the suitability of these networks for an important class of scientific problems such as matrix computation, sorting, and Fourier transforms. In this study, we present and evaluate two structural outlooks for algorithm development on OTIS-networks. The proposed structural outlooks are general in the sense that no specific factor network or problem domain is assumed. Timing models for measuring the performance of the proposed structural outlooks are provided. Through these models, the performance of various algorithms on OTIS-networks are evaluated and compared with their counterparts on conventional electronic interconnection systems. The obtained results reveal that OTIS-networks are an attractive candidate for future parallel computers due to their superior performance characteristics over networks using traditional electronic interconnects

    Simulations and Algorithms on Reconfigurable Meshes With Pipelined Optical Buses.

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    Recently, many models using reconfigurable optically pipelined buses have been proposed in the literature. A system with an optically pipelined bus uses optical waveguides, with unidirectional propagation and predictable delays, instead of electrical buses to transfer information among processors. These two properties enable synchronized concurrent access to an optical bus in a pipelined fashion. Combined with the abilities of the bus structure to broadcast and multicast, this architecture suits many communication-intensive applications. We establish the equivalence of three such one-dimensional optical models, namely the LARPBS, LPB, and POB. This implies an automatic translation of algorithms (without loss of speed or efficiency) among these models. In particular, since the LPB is the same as an LARPBS without the ability to segment its buses, their equivalence establishes reconfigurable delays (rather than segmenting ability) as the key to the power of optically pipelined models. We also present simulations for a number of two-dimensional optical models and establish that they possess the same complexity, so that any of these models can simulate a step of one of the other models in constant time with a polynomial increase in size. Specifically, we determine the complexity of three two-dimensional optical models (the PR-Mesh, APPBS, and AROB) to be the same as the well known LR-Mesh and the cycle-free LR-Mesh. We develop algorithms for the LARPBS and PR-Mesh that are more efficient than existing algorithms in part by exploiting the pipelining, segmenting, and multicasting characteristics of these models. We also consider the implications of certain physical constraints placed on the system by restricting the distance over which two processors are able to communicate. All algorithms developed for these models assume that a healthy system is available. We present some fundamental algorithms that are able to tolerate up to N/2 faults on an N-processor LARPBS. We then extend these results to apply to other algorithms in the areas of image processing and matrix operations
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