2D Detectors for Particle Physics and for Imaging Applications

The demands on detectors for particle detection as well as for medical and astronomical X-ray imaging are continuously pushing the development of novel pixel detectors. The state of the art in pixel detector technology to date are hybrid pixel detectors in which sensor and read-out integrated circuits are processed on different substrates and connected via high density interconnect structures. While these detectors are technologically mastered such that large scale particle detectors can be and are being built, the demands for improved performance for the next generation particle detectors ask for the development of monolithic or semi-monolithic approaches. Given the fact that the demands for medical imaging are different in some key aspects, developments for these applications, which started as particle physics spin-off, are becomming rather independent. New approaches are leading to novel signal processing concepts and interconnect technologies to satisfy the need for very high dynamic range and large area detectors. The present state in hybrid and (semi-)monolithic pixel detector development and their different approaches for particle physics and imaging application is reviewed

Large-Scale Optical Neural Networks based on Photoelectric Multiplication

Recent success in deep neural networks has generated strong interest in hardware accelerators to improve speed and energy consumption. This paper presents a new type of photonic accelerator based on coherent detection that is scalable to large ($N \gtrsim 10^6$) networks and can be operated at high (GHz) speeds and very low (sub-aJ) energies per multiply-and-accumulate (MAC), using the massive spatial multiplexing enabled by standard free-space optical components. In contrast to previous approaches, both weights and inputs are optically encoded so that the network can be reprogrammed and trained on the fly. Simulations of the network using models for digit- and image-classification reveal a "standard quantum limit" for optical neural networks, set by photodetector shot noise. This bound, which can be as low as 50 zJ/MAC, suggests performance below the thermodynamic (Landauer) limit for digital irreversible computation is theoretically possible in this device. The proposed accelerator can implement both fully-connected and convolutional networks. We also present a scheme for back-propagation and training that can be performed in the same hardware. This architecture will enable a new class of ultra-low-energy processors for deep learning.Comment: Text: 10 pages, 5 figures, 1 table. Supplementary: 8 pages, 5, figures, 2 table

A Radiation-Hard Dual Channel 4-bit Pipeline for a 12-bit 40 MS/s ADC Prototype with extended Dynamic Range for the ATLAS Liquid Argon Calorimeter Readout Electronics Upgrade at the CERN LHC

The design of a radiation-hard dual channel 12-bit 40 MS/s pipeline ADC with extended dynamic range is presented, for use in the readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider. The design consists of two pipeline A/D channels with four Multiplying Digital-to-Analog Converters with nominal 12-bit resolution each. The design, fabricated in the IBM 130 nm CMOS process, shows a performance of 68 dB SNDR at 18 MHz for a single channel at 40 MS/s while consuming 55 mW/channel from a 2.5 V supply, and exhibits no performance degradation after irradiation. Various gain selection algorithms to achieve the extended dynamic range are implemented and tested.Comment: 22 pages, 22 figures, accepted by JINS

Infrastructure for Detector Research and Development towards the International Linear Collider

The EUDET-project was launched to create an infrastructure for developing and testing new and advanced detector technologies to be used at a future linear collider. The aim was to make possible experimentation and analysis of data for institutes, which otherwise could not be realized due to lack of resources. The infrastructure comprised an analysis and software network, and instrumentation infrastructures for tracking detectors as well as for calorimetry.Comment: 54 pages, 48 picture

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

© 2016 Cheung, Schultz and Luk.NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation

Inverter-Based Low-Voltage CCII- Design and Its Filter Application

This paper presents a negative type second-generation current conveyor (CCII-). It is based on an inverter-based low-voltage error amplifier, and a negative current mirror. The CCII- could be operated in a very low supply voltage such as ±0.5V. The proposed CCII- has wide input voltage range (±0.24V), wide output voltage (±0.24V) and wide output current range (±24mA). The proposed CCII- has no on-chip capacitors, so it can be designed with standard CMOS digital processes. Moreover, the architecture of the proposed circuit without cascoded MOSFET transistors is easily designed and suitable for low-voltage operation. The proposed CCII- has been fabricated in TSMC 0.18μm CMOS processes and it occupies 1189.91 x 1178.43μm2 (include PADs). It can also be validated by low voltage CCII filters

A monolithic ASIC demonstrator for the Thin Time-of-Flight PET scanner

Time-of-flight measurement is an important advancement in PET scanners to improve image reconstruction with a lower delivered radiation dose. This article describes the monolithic ASIC for the TT-PET project, a novel idea for a high-precision PET scanner for small animals. The chip uses a SiGe Bi-CMOS process for timing measurements, integrating a fully-depleted pixel matrix with a low-power BJT-based front-end per channel, integrated on the same 100 $\mu{} m$ thick die. The target timing resolution is 30 ps RMS for electrons from the conversion of 511 keV photons. A novel synchronization scheme using a patent-pending TDC is used to allow the synchronization of 1.6 million channels across almost 2000 different chips at picosecond-level. A full-featured demonstrator chip with a 3x10 matrix of 500x500 $\mu{} m^{2}$ pixels was produced to validate each block. Its design and experimental results are presented here