High performance RF and baseband building blocks for wireless receivers

Because of the unique architecture of wireless receivers, a designer must understand both the high frequency aspects as well as the low-frequency analog considerations for different building blocks of the receiver. The primary goal of this research work is to explore techniques for implementing high performance RF and baseband building blocks for wireless applications. Several novel techniques to improve the performance of analog building blocks are presented. An enhanced technique to couple two LC resonators is presented which does not degrade the loaded quality factor of the resonators which results in an increased dynamic range. A novel technique to automatically tune the quality factor of LC resonators is presented. The proposed scheme is stable and fast and allows programming both the quality factor and amplitude response of the LC filter. To keep the oscillation amplitude of LC VCOs constant and thus achieving a minimum phase noise and a reliable startup, a stable amplitude control loop is presented. The proposed scheme has been also used in a master-slave quality factor tuning of LC filters. An efficient and low-cost architecture for a 3.1GHz-10.6GHz ultra-wide band frequency synthesizer is presented. The proposed scheme is capable of generating 14A novel pseudo-differential transconductance amplifier is presented. The proposed scheme takes advantage of the second-order harmonic available at the output current of pseudo-differential structure to cancel the third-order harmonic distortion. A novel nonlinear function is proposed which inherently removes the third and the fifth order harmonics at its output signal. The proposed nonlinear block is used in a bandpass-based oscillator to generate a highly linear sinusoidal output. Finally, a linearized BiCMOS transconductance amplifier is presented. This transconductance is used to build a third-order linear phase low pass filter with a cut-off frequency of 264MHz for an ultra-wide band receiver. carrier frequencies

Realization of analog signal processing modules using carbon nanotube field effect transistors

This thesis presents the realization and performance analysis of several carbon nanotube field effect transistor (CNTFET) based analog signal processing (ASP) modules. CNTFET is predicted as a possible successor to conventional silicon complementary metal oxide semiconductor (CMOS), which has reached its scaling limits. The CMOS based ASP modules face significant challenges at deep nanoscale, resulting in severe performance degradations due to short channel effects. The main goal of this work is to realize CNTFET active building blocks (ABBs), and then to utilize these ABBs for realization of low-voltage, low-power, and high-frequency ASP modules. The proposed ABBs have low power dissipation, reduced parasitic components, and minimum number of CNTFETs. The proposed modules are active inductor (AI), first-order phase shifter, and second-order phase shifter. This research proposes a new CNTFET based grounded AI (GAI) circuit with high self-resonance frequency (SRF), wide tunable inductance range, and high quality factor. Simulation results demonstrate that the GAI offers tunable inductance from 4.4 nH to 287.4 nH with a maximum SRF of 101 GHz. It consumes very low power dissipation of 0.337 mW. In comparison to high performance available GAI circuits, the proposed GAI shows 34% reduction in power dissipation and nine times higher SRF. A highfrequency low-noise amplifier (LNA) circuit is also designed by utilizing the proposed GAI to showcase its application. The simulation result shows high frequency bandwidth of 17.5 GHz to 57 GHz, 15.9 dB maximum voltage gain, better than -10 dB input matching, and less than 3 dB noise figure. This research also proposes a compact wideband first-order phase shifter (FOPS) and active-only FOPS (AOFOPS). Simulation results demonstrate the FOPS has a tunable pole frequency range between 1.913 GHz and 40.2 GHz, input and output voltage noises of 4.402 nV/VHz and 4.414 nV/VH z respectively, and power dissipation of 0.4862 mW. The AOFOPS circuit also offers a wide tunable range of pole frequency between 34.2 GHz to 56.4 GHz with input noise and output noise of 6.822 nV/VHz and 6.761 nV/VHz respectively, and power dissipation of only 0.0338 mW. The AOFOPS dissipates 12.40 times less power in comparison to state-of-art FOPS circuits. This work also proposes active-only second-order phase shifter. The proposed circuit provides a tunable pole frequency between 16.2 GHz to 42.5 GHz, with input and output noises of 21.698 nV/VHz and 21.593 nV/VHz respectively, while consuming 0.2256 mW power. All circuit performances are verified through HSPICE simulation by utilizing the Stanford CNTFET model at 16 nm technology node with supply voltage of 0.7 V

A very high speed bandpass continous time sigma delta modulator for RF receiver front end A/D conversion

Master'sMASTER OF ENGINEERIN

Design of a correlator for UWB transceivers

Master'sMASTER OF ENGINEERIN