4 research outputs found
Memory hierarchy and data communication in heterogeneous reconfigurable SoCs
The miniaturization race in the hardware industry aiming at continuous increasing
of transistor density on a die does not bring respective application performance
improvements any more. One of the most promising alternatives is to
exploit a heterogeneous nature of common applications in hardware. Supported by
reconfigurable computation, which has already proved its efficiency in accelerating
data intensive applications, this concept promises a breakthrough in contemporary
technology development.
Memory organization in such heterogeneous reconfigurable architectures becomes
very critical. Two primary aspects introduce a sophisticated trade-off. On
the one hand, a memory subsystem should provide well organized distributed data
structure and guarantee the required data bandwidth. On the other hand, it should
hide the heterogeneous hardware structure from the end-user, in order to support
feasible high-level programmability of the system.
This thesis work explores the heterogeneous reconfigurable hardware architectures
and presents possible solutions to cope the problem of memory organization
and data structure. By the example of the MORPHEUS heterogeneous platform,
the discussion follows the complete design cycle, starting from decision making
and justification, until hardware realization. Particular emphasis is made on the
methods to support high system performance, meet application requirements, and
provide a user-friendly programmer interface.
As a result, the research introduces a complete heterogeneous platform enhanced
with a hierarchical memory organization, which copes with its task by
means of separating computation from communication, providing reconfigurable
engines with computation and configuration data, and unification of heterogeneous
computational devices using local storage buffers. It is distinguished from the
related solutions by distributed data-flow organization, specifically engineered
mechanisms to operate with data on local domains, particular communication infrastructure
based on Network-on-Chip, and thorough methods to prevent computation
and communication stalls. In addition, a novel advanced technique to accelerate
memory access was developed and implemented
An innovative vision system for industrial applications
Tesis doctoral inédita leída en la Universidad Autónoma de Madrid, Escuela Politécnica Superior, Departamento de Tecnología Electrónica y de las Comunicaciones. Fecha de lectura: 20-11-2015A pesar de que los sistemas de visión por computadora ocupan un
puesto predominante en nuestra sociedad, su estructura no sigue ningún
estándar. La implementación de aplicaciones de visión requiere de plataformas
de alto rendimiento tales como GPUs o FPGAs y el uso de sensores
de imagen con características muy distintas a las de la electrónica
de consumo. En la actualidad, cada fabricante y equipo de investigación
desarrollan sus plataformas de visión de forma independiente y sin
ningún tipo de intercompatibilidad. En esta tesis se presenta una nueva
plataforma de visión por computador utilizable en un amplio espectro
de aplicaciones. Las características de dicha plataforma se han definido
tras la implementación de tres aplicaciones de visión, basadas en: SOC,
FPGA y GPU, respectivamente. Como resultado, se ha definido una
plataforma modular con los siguientes componentes intercambiables:
Sensor, procesador de imágenes ”al vuelo”, unidad de procesado principal,
acelerador hardware y pila de software. Asimismo, se presenta
un algoritmo para realizar transformaciones geométricas, sintetizable en
FPGA y con una latencia de tan solo 90 líneas horizontales. Todos los
elementos software de esta plataforma están desarrollados con licencias
de Software Libre; durante el trascurso de esta tesis se han contribuido
y aceptado más de 200 cambios a distintos proyectos de Software Libre,
tales como: Linux, YoctoProject y U-boot, entre otros, promoviendo el
ecosistema necesario para la creación de una comunidad alrededor de
esta tesis.Tras la implementación de la plataforma en un producto comercial,
Qtechnology QT5022, y su uso en varias aplicaciones industriales
se ha demostrado que es posible el uso de una plataforma genérica de
visión que permita reutilizar elementos y comparar resultados objetivamenteDespite the fact that computer vision systems place an important role in
our society, its structure does not follow any standard. The implementation
of computer vision application require high performance platforms,
such as GPUs or FPGAs, and very specialized image sensors. Nowadays,
each manufacturer and research lab develops their own vision platform
independently without considering any inter-compatibility. This Thesis
introduces a new computer vision platform that can be used in a wide
spectrum of applications. The characteristics of the platform has been
defined after the implementation of three different computer vision applications,
based on: SOC, FPGA and GPU respectively. As a result, a
new modular platform has been defined with the following interchangeably
elements: Sensor, Image Processing Pipeline, Processing Unit, Acceleration
unit and Computer Vision Stack. This thesis also presents
an FPGA synthetizable algorithm for performing geometric transformations
on the fly, with a latency under 90 horizontal lines. All the software
elements of this platform have an Open Source licence; over the course
of this thesis, more than 200 patches have been contributed and accepted
into different Open Source projects like the Linux Kernel, Yocto Project
and U-boot, among others, promoting the required ecosystem for the
creation of a community around this novel system. The platform has
been validated in an industrial product, Qtechnology QT5022, used on
diverse industrial applications; demonstrating the great advantages of a
generic computer vision system as a platform for reusing elements and
comparing results objectivel