Homomorphic Data Isolation for Hardware Trojan Protection

The interest in homomorphic encryption/decryption is increasing due to its excellent security properties and operating facilities. It allows operating on data without revealing its content. In this work, we suggest using homomorphism for Hardware Trojan protection. We implement two partial homomorphic designs based on ElGamal encryption/decryption scheme. The first design is a multiplicative homomorphic, whereas the second one is an additive homomorphic. We implement the proposed designs on a low-cost Xilinx Spartan-6 FPGA. Area utilization, delay, and power consumption are reported for both designs. Furthermore, we introduce a dual-circuit design that combines the two earlier designs using resource sharing in order to have minimum area cost. Experimental results show that our dual-circuit design saves 35% of the logic resources compared to a regular design without resource sharing. The saving in power consumption is 20%, whereas the number of cycles needed remains almost the sam

Silicon-based distributed voltage-controlled oscillators

Distributed voltage-controlled oscillators (DVCOs) are presented as a new approach to the design of silicon VCOs at microwave frequencies. In this paper, the operation of distributed oscillators is analyzed and the general oscillation condition is derived, resulting in analytical expressions for the frequency and amplitude. Two tuning techniques for DVCOs are demonstrated, namely, the inherent-varactor tuning and delay-balanced current-steering tuning. A complete analysis of the tuning techniques is presented. CMOS and bipolar DVCOs have been designed and fabricated in a 0.35-μm BiCMOS process. A 10-GHz CMOS DVCO achieves a tuning range of 12% (9.3-10.5 GHz) and a phase noise of -103 dBc/Hz at 600 kHz offset from the carrier. The oscillator provides an output power of -4.5 dBm without any buffering, drawing 14 mA of dc current from a 2.5-V power supply. A 12-GHz bipolar DVCO consuming 6 mA from a 2.5-V power supply is also demonstrated. It has a tuning range of 26% with a phase noise of -99 dBc/Hz at 600 kHz offset from the carrier

A 5.0 Ghz Active Inductor Current Controlled Oscillator

The demand for wireless communications in the field of voice and data has rapidly grown. The integration level of Radio Frequency (RF) transceiver systems have become very intricate and efforts to deal with this has risen almost exponentially. Communications nowadays require system with extreme speeds to cater for high speed applications such as 4G and 5G, wider tuning range to cater for variety of applications, minimal timing errors and lower cost. Oscillators play the key role in determining the quality of the RF communications system. Most oscillators are voltage based and known as Voltage Controlled Oscillator (VCO) and comes mainly in two types, which are LC Tank Oscillators and Non LC-Tank Oscillators. The former is very good for lower phase noise due the usage of passive inductor. The latter such as ring oscillators are much smaller in size than LC-Tank, thus lower cost, but exhibit much higher phase noise. However, current sources are becoming more popular and employed in oscillator to form Current Controlled Oscillator (CCO) due to its higher frequency as compared to voltage source. Hence the goal has been put forth to design a CCO that produces 5 GHz center frequency, tuning range of 500 MHz and with phase noise better than -110 dBc/Hz by employing active inductor. To demonstrate the proposed concept, 5-stage ring oscillator with active inductor design controlled by a current-mode circuit, were designed and ran through simulation using 180 nm CMOS technology provided by Silterra. The work proceeds to validate and make improvements to the fundamental performance parameters of a local oscillator design that incorporates dual delay path, negative skewed delay, current source, cross-coupled transistors and active inductor. Analysis were done on how the cross-coupled transistors play a role in affecting the distinctive frequency operation pattern. Results from the simulation show that the oscillator’s maximum frequency obtained without distortion is 5.81 GHz. The cross coupled MOS transistors and active inductor controlled by current source aided well in improving the oscillator’s phase noise and frequency. Various simulation results show that the frequency range of this 5-stage oscillator runs between 3.87 GHz to 5.81 GHz. The critical parameter of any oscillator, which is the phase noise, is -113.2 dBc/Hz at 1 MHz offset with a center frequency of 5.81 GHz. The performance of this new design has improved, in general, about 36% on the frequency while 8% on the phase noise as compared with the non-LC Tank topology. Apart from the frequency and phase noise, the output power and size of this design is 9.41 dBm and 0.22 mm2 respectively. This is an improvement of 53% on the output power and 33% on the size when comparing with the non-LC Tank topology. Conclusively this design has successfully achieved the goals set forth for this research

High Speed CMOS VCO For Advanced Communications [TK7871.99.M99 C435 2003 f rb][Microfiche 7271].

Peningkatan keperluan bagi komunikasi tanpa wayar dalam suara dan data telah memotivasikan kerja-kerja untuk meningkatkan tahap intregrasi dalam pemancar-penerima berfrekuensi radio (RF) baru-baru ini. The fast growing demand of wireless communications for voice and data has driven recent efforts to dramatically increase the level of integration in RF transceivers

CMOS ring oscillator delay cell performance: a comparative study

A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell

DESIGN OF A FOUR STAGES VCO USING A NOVEL DELAY CIRCUIT FOR OPERATION IN DISTRIBUTED BAND FREQUENCIES

The manuscript proposes a novel architecture of a delay cell that is implemented in 4-stage VCO which has the ability to operate in two distributed frequency bands. The operating frequency is chosen based on the principle of carrier mobility and the transistor resistance. The VCO uses dual delay input techniques to improve the frequency of operation. The design is implemented in Cadence 90nm GPDK CMOS technology and simulated results show that it is capable of operating in dual frequency bands of 55 MHz to 606 MHz and 857 MHz to 1049 MHz. At normal temperature (270) power consumption of the circuit is found to be 151μW at 606 MHz and 157μW at 1049 MHz respectively and consumes an area of 171.42µm2. The design shows good tradeoff between the parameters-operating frequency, phase noise and power consumption

Ring oscillator clocks and margins

How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA machinery for timing analysis and sign-off. The paper is based on the study of the margins of a ring oscillator that substitutes a PLL as clock generator. A timing model is proposed that shows that a 12% margin for delay lines can be sufficient to cover variability in a 65nm technology. In a typical scenario, performance and energy improvements between 15% and 35% can be obtained by using a ring oscillator instead of a PLL. The paper concludes that a synchronous circuit with a ring oscillator clock shows similar benefits in performance and energy as those of bundled-data asynchronous circuits.Peer ReviewedPostprint (author's final draft

A New Technique for the Design of Multi-Phase Voltage Controlled Oscillators

© 2017 World Scientific Publishing Company.In this work, a novel circuit structure for second-harmonic multi-phase voltage controlled oscillator (MVCO) is presented. The proposed MVCO is composed of (Formula presented.) ((Formula presented.) being an integer number and (Formula presented.)2) identical inductor–capacitor ((Formula presented.)) tank VCOs. In theory, this MVCO can provide 2(Formula presented.) different phase sinusoidal signals. A six-phase VCO based on the proposed structure is designed in a TSMC 0.18(Formula presented.)um CMOS process. Simulation results show that at the supply voltage of 0.8(Formula presented.)V, the total power consumption of the six-phase VCO circuit is about 1(Formula presented.)mW, the oscillation frequency is tunable from 2.3(Formula presented.)GHz to 2.5(Formula presented.)GHz when the control voltage varies from 0(Formula presented.)V to 0.8(Formula presented.)V, and the phase noise is lower than (Formula presented.)128(Formula presented.)dBc/Hz at 1(Formula presented.)MHz offset frequency. The proposed MVCO has lower phase noise, lower power consumption and more outputs than other related works in the literature.Peer reviewedFinal Accepted Versio