Design and testing methodologies for signal processing systems using DICE

The design and integration of embedded systems in heterogeneous programming environments is still largely done in an ad hoc fashion making the overall development process more complicated, tedious and error-prone. In this work, we propose enhancements to existing design flows that utilize model-based design to verify cross-platform correctness of individual actors. The DSPCAD Integrative Command Line Environment (DICE) is a realization of managing these enhancements. We demonstrate this design flow with two case studies. By using DICE's novel test framework on modules of a triggering system in the Large Hadron Collider, we demonstrate how the cross-platform model-based approach, automatic testbench creation and integration of testing in the design process alleviate the rigors of developing such a complex digital system. The second case study is an exploration study into the required precision for eigenvalue decomposition using the Jacobi algorithm. This case study is a demonstration of the use of dataflow modeling in early stage application exploration and the use of DICE in the overall design flow

Image Processing Using Dataflow Techniques

Corner detection is an important task in digital image processing. Corner detection algorithms are widely used in pattern recognition, image mosaicing, motion detection, etc. The implementations of such algorithm in software/hardware can be challenging. One classical algorithm for finding corners in images is proposed by Harris and Stephens in 1988, commonly known as Harris corner detection algorithm; There have been different implementations of the algorithm in OpenCV and on FPGA. The implementations of the algorithm in hardware have been relatively less, and most importantly the architectures of the algorithm on FPGA have relatively been unexplored. LIDE, created at University of Maryland, College Park, is a light-weight dataflow environment for rapid prototyping of DSP systems using dataflow techniques. The framework in C programming language is called LIDE-C, in Verilog HDL is called LIDE-V. This light-weight framework makes modeling of DSPs easy in both software and hardware. It is platform- and language-agnostic. This thesis work models the application both in LIDE-C and LIDE-V, our emphasis is, however, to propose multi-architecture corner detection Harris algorithm in LIDE-V. In LIDE, computations are distributed to different computation nodes in dataflow graphs. Each node is called actor in LIDE, and each actor has different modes of computation. Depending on how we construct a dataflow graph for an application and how we design actors of a dataflow graph, we easily create different implementations for the same algorithm. In this thesis, different hardware architecture of the Harris algorithm will be proposed with different latency, resource usage, and throughput characteristics. Our preliminary results reveal, among other things, that unfolding for the non-max suppression actor not only improve performance but also decrease resource usage

DESIGN OPTIMIZATION OF EMBEDDED SIGNAL PROCESSING SYSTEMS FOR TARGET DETECTION

Sensor networks for automated detection of targets, such as pedestrians and vehicles, are highly relevant in defense and surveillance applications. For this purpose, a variety of target detection algorithms and systems using different types of sensors have been proposed in the literature. Among them, systems based on non-image sensors are of special interest in many practical deployment scenarios because of their power efficiency and low computational loads. In this thesis, we investigate low power sensor systems for detecting people and vehicles using non-image sensors such as acoustic and seismic sensors. Our investigation is focused on design optimization across trade-offs including real-time performance, energy efficiency, and target detection accuracy, which are key design evaluation metrics for this class of systems. Design and implementation of low power, embedded target detection systems can be decomposed into two major, inter-related subproblems: (a) algorithm development, which encompasses the development or selection of detection algorithms and optimization of their parameters, and (b) system development, which involves the mapping of the algorithms derived from (a) into real-time, energy efficient implementations on the targeted embedded platforms. In this thesis, we address both of these subproblems in an integrated manner. That is, we investigate novel algorithmic techniques for improvement of accuracy without excessive computational complexity, and we develop new design methodologies, tools, and implementations for efficient realization of target detection algorithms on embedded platforms. We focus specifically on target detection systems that employ acoustic and seismic sensing modalities. These selected modalities support the low power design objectives of our work. However, we envision that our developed algorithms and implementation techniques can be extended readily to other types or combinations of relevant sensing modalities. Throughout this research, we have developed prototypes of our new algorithms and design methods on embedded platforms, and we have experimented with these prototypes to demonstrate our findings, and iteratively improve upon the achieved implementation trade-offs. The main contributions of this thesis are summarized in the following. (1). Classification algorithm for acoustic and seismic signals. We have developed a new classification algorithm for discrimination among people, vehicles, and noise. The algorithm is based on a new fusion technique for acoustic and seismic signals. Our new fusion technique was evaluated through experiments using actual measured datasets, which were collected from different sensors installed in different locations and at different times of day. Our proposed classification algorithm was shown to achieve a significant reduction in the number of false alarms compared to a baseline fusion approach. (2). Joint target localization and classification framework using sensor networks. We designed a joint framework for target localization and classification using a single generalized model for non-imaging based multi- modal sensor data. For target localization, we exploited both sensor data and estimated dynamics within a local neighborhood. We validated the capabilities of our framework by using an actual multi-modal dataset, which includes ground truth GPS information (e.g., time and position) and data from co-located seismic and acoustic sensors. Experimental results showed that our framework achieves better classification accuracy compared to state of the art fusion algorithms using temporal accumulation and achieves more accurate target localizations than a baseline target localization approach. (3). Design and optimization of target detection systems on embedded platforms using dataflow methods. We developed a foundation for our system-level design research by introducing a new rapid prototyping methodology and associated software tool. Using this tool, we presented the design and implementation of a novel, multi-mode embedded signal processing system for detection of people and vehicles related to our algorithmic contributions. We applied a strategically-configured suite of single- and dual-modality signal processing techniques together with dataflow-based design optimization for energy-efficient, real-time implementation. Through experiments using a Raspberry Pi platform, we demonstrated the capability of our target detection system to provide efficient operational trade-offs among detection accuracy, energy efficiency, and processing speed. (4). Software synthesis from dataflow schedule graphs on multicore platforms. We developed new software synthesis methods and tools for design and implementation of embedded signal processing systems using dataflow schedule graphs (DSGs). DSGs provide formal representations of dataflow schedules, which encapsulate information about the assignment of computational tasks (signal processing modules) to processing resources and the ordering of tasks that are assigned to the same resource. Building on fundamental DSG modeling concepts from the literature, we developed the first algorithms and supporting software synthesis tools for mapping DSG representations into efficient multi-threaded implementations. Our tools replace ad-hoc multicore signal processing system development processes with a structured process that is rooted in dataflow formalisms and supported with a high degree of automation. We evaluated our new DSG methods and tools through a demonstration involving multi-threaded implementation of our proposed classification algorithm and associated fusion technique for acoustic/seismic signals

The DSPCAD Lightweight Dataflow Environment: Introduction to LIDE Version 0.1

LIDE (the DSPCAD Lightweight Dataflow Environment) is a flexible, lightweight design environment that allows designers to experiment with dataflow-based approaches for design and implementation of digital signal processing (DSP) systems. LIDE contains libraries of dataflow graph elements (primitive actors, hierarchical actors, and edges) and utilities that assist designers in modeling, simulating, and implementing DSP systems using formal dataflow techniques. The libraries of dataflow graph elements (mainly actors) contained in LIDE provide useful building blocks that can be used to construct signal processing applications, and that can be used as examples that designers can adapt to create their own, customized LIDE actors. Furthermore, by using LIDE along with the DSPCAD Integrative Command Line Environment (DICE), designers can efficiently create and execute unit tests for user-designed actors. This report provides an introduction to LIDE. The report includes details on the process for setting up the LIDE environment, and covers methods for using pre-designed libraries of graph elements, as well as creating user-designed libraries and associated utilities using the C language. The report also gives an introduction to the C language plug-in for dicelang. This plug-in, called dicelang-C, provides features for efficient C-based project development and maintenance that are useful to apply when working with LIDE

OpenDF - A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems

International audienceThis paper presents the OpenDF framework and recalls that dataflow programming was once invented to address the problem of parallel computing. We discuss the problems with an imperative style, von Neumann programs, and present what we believe are the advantages of using a dataflow programming model. The CAL actor language is briefly presented and its role in the ISO/MPEG standard is discussed. The Dataflow Interchange Format (DIF) and related tools can be used for analysis of actors and networks, demonstrating the advantages of a dataflow approach. Finally, an overview of a case study implementing an MPEG-4 decoder is given

Advances in Architectures and Tools for FPGAs and their Impact on the Design of Complex Systems for Particle Physics

The continual improvement of semiconductor technology has provided rapid advancements in device frequency and density. Designers of electronics systems for high-energy physics (HEP) have benefited from these advancements, transitioning many designs from fixed-function ASICs to more flexible FPGA-based platforms. Today’s FPGA devices provide a significantly higher amount of resources than those available during the initial Large Hadron Collider design phase. To take advantage of the capabilities of future FPGAs in the next generation of HEP experiments, designers must not only anticipate further improvements in FPGA hardware, but must also adopt design tools and methodologies that can scale along with that hardware. In this paper, we outline the major trends in FPGA hardware, describe the design challenges these trends will present to developers of HEP electronics, and discuss a range of techniques that can be adopted to overcome these challenges

Synthesis of Embedded Software using Dataflow Schedule Graphs

In the design and implementation of digital signal processing (DSP) systems, dataflow is recognized as a natural model for specifying applications, and dataflow enables useful model-based methodologies for analysis, synthesis, and optimization of implementations. A wide range of embedded signal processing applications can be designed efficiently using the high level abstractions that are provided by dataflow programming models. In addition to their use in parallelizing computations for faster execution, dataflow graphs have additional advantages that stem from their modularity and formal foundation. An important problem in the development of dataflow-based design tools is the automated synthesis of software from dataflow representations. In this thesis, we develop new software synthesis techniques for dataflow based design and implementation of signal processing systems. An important task in software synthesis from dataflow graphs is that of {\em scheduling}. Scheduling refers to the assignment of actors to processing resources and the ordering of actors that share the same resource. Scheduling typically involves very complex design spaces, and has a significant impact on most relevant implementation metrics, including latency, throughput, energy consumption, and memory requirements. In this thesis, we integrate a model-based representation, called the {\em dataflow schedule graph} ({\em DSG}), into the software synthesis process. The DSG approach allows designers to model a schedule for a dataflow graph as a separate dataflow graph, thereby providing a formal, abstract (platform- and language-independent) representation for the schedule. While we demonstrate this DSG-integrated software synthesis capability by translating DSGs into OpenCL implementations, the use of a model-based schedule representation makes the approach readily retargetable to other implementation languages. We also investigate a number of optimization techniques to improve the efficiency of software that is synthesized from DSGs. Through experimental evaluation of the generated software, we demonstrate the correctness and efficiency of our new techniques for dataflow-based software synthesis and optimization

Dataflow-Based Implementation of Deep Learning Application

The proliferation of research on high efficient performance on deep learning has contributed to an increasing challenge and interest in the topic concerning the integration of this advanced-technology into daily life. Although a large amount of work on the domain of machine learning has been dedicated to the accuracy, efficiency, net topology and algorithm in the training and recognition procedures, the investigation of deep learning implementations in highly resource-constrainted contexts has been relatively unexplored due to the large computational requirements involved during the process of training large-scale network. In light of this, one process concentrated on parameters extraction and dataflow design, implementation, optimization of one deep learning application for vehicle classification on multicore platforms with limited numbers of available processor cores is demonstrated. By means of thousands of actors computation and fifos communication, we establish one enormous and complex dataflow graph, and then using the resulting dataflow representations, we apply a wide range of design optimizations to probe efficient implementations on three different multicore platforms. Through the incorporation of dataflow techniques, it is gratifying for us to see its effectiveness and efficiency in the several flexible experiments with alternative platforms that tailored to the resource constraints. Besides, we pioneer three general, novel, primitive and thorough flow charts during the work - deep leanring model, LIDE-C establishing model, LIDE-C coding model. Finally, not only LIDE-C we utilize for the implementation, but also DICE we apply for validation and verification. Both tools are incubated by DSPCAD at Maryland of University, and will be updated better in the future

Overview of the MPEG Reconfigurable Video Coding Framework

International audienceVideo coding technology in the last 20 years has evolved producing a variety of different and complex algorithms and coding standards. So far the specification of such standards, and of the algorithms that build them, has been done case by case providing monolithic textual and reference software specifications in different forms and programming languages. However, very little attention has been given to provide a specification formalism that explicitly presents common components between standards, and the incremental modifications of such monolithic standards. The MPEG Reconfigurable Video Coding (RVC) framework is a new ISO standard currently under its final stage of standardization, aiming at providing video codec specifications at the level of library components instead of monolithic algorithms. The new concept is to be able to specify a decoder of an existing standard or a completely new configuration that may better satisfy application-specific constraints by selecting standard components from a library of standard coding algorithms. The possibility of dynamic configuration and reconfiguration of codecs also requires new methodologies and new tools for describing the new bitstream syntaxes and the parsers of such new codecs. The RVC framework is based on the usage of a new actor/ dataflow oriented language called CAL for the specification of the standard library and instantiation of the RVC decoder model. This language has been specifically designed for modeling complex signal processing systems. CAL dataflow models expose the intrinsic concurrency of the algorithms by employing the notions of actor programming and dataflow. The paper gives an overview of the concepts and technologies building the standard RVC framework and the non standard tools supporting the RVC model from the instantiation and simulation of the CAL model to software and/or hardware code synthesis