Observability analysis of sensorless synchronous machine drives

This paper studies the local observability of synchronous machines using a unified approach. Recently, motion sensorless control of electrical drives has gained high interest. The main challenge for such a technology is the poor performance in some operation conditions. One interesting theory that helps understanding the origin of this problem is the observability analysis of nonlinear systems. In this paper, the observability of the wound-rotor synchronous machine is studied. The results are extended to other synchronous machines, adopting a unified analysis. Furthermore, a high-frequency injection-based technique is proposed to enhance the sensorless operation of the wound-rotor synchronous machine at standstill

Formalization and Correctness of the PALS Architectural Pattern for Distributed Real-Time Systems

Many Distributed Real-Time Systems (DRTS), such as integrated modular avionics systems and distributed control systems in motor vehicles, are made up of a collection of components communicating asynchronously among themselves and with their environment that must change their state and respond to environment inputs within hard real-time bounds. Such systems are often safety-critical and need to be certi???ed; but their certi???cation is currently very hard due to their distributed nature. The Physically Asynchronous Logically Synchronous (PALS) architectural pattern can greatly reduce the design and veri???cation complexities of achieving virtual synchrony in a DTRS. This work presents a formal speci???cation of PALS as a formal model transformation that maps a synchronous design, together with a set of performance bounds of the underlying infrastructure, to a formal DRTS speci???cation that is semantically equivalent to the synchronous design. This semantic equivalence is proved, showing that the formal veri???cation of temporal logic properties of the DRTS can be reduced to their veri???cation on the much simpler synchronous design. An avionics system case study is used to illustrate the usefulness of PALS for formal verification purposes.unpublishednot peer reviewe

Integration of a mean-torque diesel engine model into a hardware-in-the-loop shipboard network simulation using lambda tuning

This study describes the creation of a hardware-in-the-loop (HIL) environment for use in evaluating network architecture, control concepts and equipment for use within marine electrical systems. The environment allows a scaled hardware network to be connected to a simulation of a multi-megawatt marine diesel prime mover, coupled via a synchronous generator. This allows All-Electric marine scenarios to be investigated without large-scale hardware trials. The method of closing the loop between simulation and hardware is described, with particular reference to the control of the laboratory synchronous machine, which represents the simulated generator(s). The fidelity of the HIL simulation is progressively improved in this study. First, a faster and more powerful field drive is implemented to improve voltage tracking. Second, the phase tracking is improved by using two nested proportional–integral–derivative–acceleration controllers for torque control, tuned using lambda tuning. The HIL environment is tested using a scenario involving a large constant-power load step. This provides a very severe test of the HIL environment, and also reveals the potentially adverse effects of constant-power loads within marine power systems

Asynchronous techniques for system-on-chip design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed

Analytical BER Performance of DS-CDMA Ad Hoc Networks using Large Area Synchronized Spreading Codes

The family of operational CDMA systems is interference-limited owing to the Inter Symbol Interference (ISI) and the Multiple Access Interference (MAI) encountered. They are interference-limited, because the orthogonality of the spreading codes is typically destroyed by the frequency-selective fading channel and hence complex multiuser detectors have to be used for mitigating these impairments. By contrast, the family of Large Area Synchronous (LAS) codes exhibits an Interference Free Window (IFW), which renders them attractive for employment in cost-efficient quasi-synchronous ad hoc networks dispensing with power control. In this contribution we investigate the performance of LAS DS-CDMA assisted ad hoc networks in the context of a simple infinite mesh of rectilinear node topology and benchmark it against classic DS-CDMA using both random spreading sequences as well as Walsh-Hadamard and Orthogonal Gold codes. It is demonstrated that LAS DS-CDMA exhibits a significantly better performance than the family of classic DS-CDMA systems operating in a quasi-synchronous scenario associated with a high node density, a low number of resolvable paths and a sufficiently high number of RAKE receiver branches