3,475 research outputs found
CVM: Crossbar-based circuit Verification through Modeling
The implementation of Boolean functions using Nano crossbar-based switching lattices has been suggested as a substitute for conventional CMOS-based approaches in digital circuits. This alternative may satisfy the needs of future electronic designs, considering the expected end of Moore’s law. This study introduces CVM, a Crossbar-based circuit Verification through Modeling technique.Lattice Science Publication (LSP)
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Implementing Boolean Functions with switching lattice networks
Four terminal switching network is an alternative structure to realize the
logic functions in electronic circuit modeling. This network can be used to
implement a Boolean function with less number of switches than the two terminal
based CMOS switch. Each switch of the network is driven by a Boolean literal.
Any switch is connected to its four neighbors if a literal takes the value 1 ,
else it is disconnected. In our work, we aimed to develop a technique by which
we can find out if any Boolean function can be implemented with a given
four-terminal network. It is done using the path of any given lattice network.
First, we developed a synthesis tool by which we can create a library of
Boolean functions with a given four-terminal switching network and random
Boolean literals. This tool can be used to check the output of any lattice
network which can also function as a lattice network solver. In the next step,
we used the library functions to develop and test our MAPPING tool where the
functions were given as input and from the output, we can get the implemented
function in four terminal lattice network. Finally, we have proposed a
systematic procedure to implement any Boolean function with a efficient way by
any given one type of lattice network
Minimalist's Linux Cluster
Using barebone PC components and NIC's, we construct a linux cluster which
has 2-dimensional mesh structure. This cluster has smaller footprint, is less
expensive, and use less power compared to conventional linux cluster. Here, we
report our experience in building such a machine and discuss our current
lattice project on the machine.Comment: 3 pages, 2 figures, Proceedings of the Lattice 03 Conference
(Tsukuba, Japan
A wideband linear tunable CDTA and its application in field programmable analogue array
This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio
Fully electrically read-write device out of a ferromagnetic semiconductor
We report the realization of a read-write device out of the ferromagnetic
semiconductor (Ga,Mn)As as the first step to fundamentally new information
processing paradigm. Writing the magnetic state is achieved by current-induced
switching and read-out of the state is done by the means of the tunneling
anisotropic magneto resistance (TAMR) effect. This one bit demonstrator device
can be used to design a electrically programmable memory and logic device.Comment: 4 pages, 4 figure
Identifying Worst-Case Test Vectors for Delay Failures Induced by Total Dose in Flash- based FPGA
A thesis presented on the effects of space radiation on the flash-based FPGA leading to failure with applying a proposed fault model to identify the worst, nominal and best-case test vectors for each. This thesis analyzed the delay failure induced in a flash-based field programmable gate array (FPGA) by a total-ionizing dose. It then identified the different factors contributing to the amount of delay induced by the total dose in the FPGA. A novel fault model for delay failure in FPGA was developed. This fault model was used to identify worst-case test vectors for delay failures induced in FPGA devices exposed to a total ionizing dose. The fault model and the methodology for identifying worst-case test vectors WCTV were validated using Micro-semi ProASIC3 FPGA and Cobalt 60 radiation facility
Towards realistic implementations of a Majorana surface code
Surface codes have emerged as promising candidates for quantum information
processing. Building on the previous idea to realize the physical qubits of
such systems in terms of Majorana bound states supported by topological
semiconductor nanowires, we show that the basic code operations, namely
projective stabilizer measurements and qubit manipulations, can be implemented
by conventional tunnel conductance probes and charge pumping via
single-electron transistors, respectively. The simplicity of the access scheme
suggests that a functional code might be in close experimental reach.Comment: 5 pages, 1 p. suppl.mat, PRL in pres
Specifications, quality control, manufacturing, and testing of accelerator magnets
The performance of the magnets plays an important role in the functioning of
an accelerator. Most of the magnets are designed at the accelerator laboratory
and built by industry. The link between the laboratory and the manufacturer is
the contract containing the Technical Specifications of the magnets. For an
overview of the contents of the Technical Specifications, the specifications
for the magnets of ALBA (bending, quadrupole, and sextupole) are described in
this paper. The basic rules of magnet design are reviewed in Appendix A.Comment: 41 pages, presented at the CERN Accelerator School CAS 2009:
Specialised Course on Magnets, Bruges, 16-25 June 200
Testability of Switching Lattices in the Cellular Fault Model
A switching lattice is a two-dimensional array of four-terminal switches implemented in its cells. Each switch is linked to the four neighbors and is connected with them when the switch is ON, or is disconnected when the switch is OFF. Recently, with the advent of a variety of emerging nanoscale technologies based on regular arrays of switches, lattices of multi-terminal switches, originally introduced by Akers in 1972, have found a renewed interest. In this paper, the testability under the Cellular Fault Model (CFM) of switching lattices is defined and analyzed. Moreover, some techniques for improving the testability of lattices are discussed and experimentally evaluated
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