Verification of the FtCayuga fault-tolerant microprocessor system. Volume 1: A case study in theorem prover-based verification

The design and formal verification of a hardware system for a task that is an important component of a fault tolerant computer architecture for flight control systems is presented. The hardware system implements an algorithm for obtaining interactive consistancy (byzantine agreement) among four microprocessors as a special instruction on the processors. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, provided certain preconditions hold. An assumption is made that the processors execute synchronously. For verification, the authors used a computer aided design hardware design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover

Structure of computations in parallel complexity classes

Issued as Annual report, and Final project report, Project no. G-36-67

On the expressive power of permanents and perfect matchings of matrices of bounded pathwidth/cliquewidth

Some 25 years ago Valiant introduced an algebraic model of computation in order to study the complexity of evaluating families of polynomials. The theory was introduced along with the complexity classes VP and VNP which are analogues of the classical classes P and NP. Families of polynomials that are difficult to evaluate (that is, VNP-complete) includes the permanent and hamiltonian polynomials. In a previous paper the authors together with P. Koiran studied the expressive power of permanent and hamiltonian polynomials of matrices of bounded treewidth, as well as the expressive power of perfect matchings of planar graphs. It was established that the permanent and hamiltonian polynomials of matrices of bounded treewidth are equivalent to arithmetic formulas. Also, the sum of weights of perfect matchings of planar graphs was shown to be equivalent to (weakly) skew circuits. In this paper we continue the research in the direction described above, and study the expressive power of permanents, hamiltonians and perfect matchings of matrices that have bounded pathwidth or bounded cliquewidth. In particular, we prove that permanents, hamiltonians and perfect matchings of matrices that have bounded pathwidth express exactly arithmetic formulas. This is an improvement of our previous result for matrices of bounded treewidth. Also, for matrices of bounded weighted cliquewidth we show membership in VP for these polynomials.Comment: 21 page

Asynchronous design of a multi-dimensional logarithmic number system processor for digital hearing instruments.

This thesis presents an asynchronous Multi-Dimensional Logarithmic Number System (MDLNS) processor that exhibits very low power dissipation. The target application is for a hearing instrument DSP. The MDLNS is a newly developed number system that has the advantage of reducing hardware complexity compared to the classical Logarithmic Number System (LNS). A synchronous implementation of a 2-digit 2DLNS filterbank, using the MDLNS to construct a FIR filterbank, has successfully proved that this novel number representation can benefit this digital hearing instrument application in the requirement of small size and low power. In this thesis we demonstrate that the combination of using the MDLNS, along with an asynchronous design methodology, produces impressive power savings compared to the previous synchronous design. A 4-phase bundled-data full-handshaking protocol is applied to the asynchronous control design. We adopt the Differential Cascade Voltage Switch Logic (DCVSL) circuit family for the design of the computation cells in this asynchronous MDLNS processor. Besides the asynchronous design methodology, we also use finite ring calculations to reduce adder bit-width to provide improvements compared to the previous MDLNS filterbank architecture. Spectre power simulation results from simulations of this asynchronous MDLNS processor demonstrate that over 70 percent power savings have been achieved compared to the synchronous design. This full-custom asynchronous MDLNS processor has been submitted for fabrication in the TSMC 0.18mum CMOS technology. A further contribution in this thesis is the development of a novel synchronizing method of design for testability (DfT), which is offered as a possible solution for asynchronous DfT methods.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .W85. Source: Masters Abstracts International, Volume: 43-01, page: 0288. Advisers: G. A. Jullien; W. C. Miller. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

Better Complexity Bounds for Cost Register Automata

Cost register automata (CRAs) are one-way finite automata whose transitions have the side effect that a register is set to the result of applying a state-dependent semiring operation to a pair of registers. Here it is shown that CRAs over the tropical semiring (N U {infinity},min,+) can simulate polynomial time computation, proving along the way that a naturally defined width-k circuit value problem over the tropical semiring is P-complete. Then the copyless variant of the CRA, requiring that semiring operations be applied to distinct registers, is shown no more powerful than NC^1 when the semiring is (Z,+,x) or (Gamma^*,max,concat). This relates questions left open in recent work on the complexity of CRA-computable functions to long-standing class separation conjectures in complexity theory, such as NC versus P and NC^1 versus GapNC^1