NASA IceCube: CubeSat Demonstration of a Commercial 883-GHz Cloud Radiometer

On April 18 2017, NASA Goddard Space Flight Center’s IceCube 3U CubeSat was launched by an ATLAS V rocket from Cape Canaveral Air Force Station on board a Cygnus resupply spacecraft, as part of NASA’s CubeSat Launch Initiative. Onboard IceCube was an 883 GHz radiometer tuned to detecting ice content in clouds, marking the first time such frequency was used from low-Earth orbit. IceCube successfully demonstrated retrieval of ice water path, generating the first ever global cloud ice map at 883 GHz. Its success provides valuable lessons on how to approach a severely resource-limited space mission and provides great insight into how this experience can be applied to future high-risk, “non-class” missions for NASA and others. IceCube marks the first official NASA Earth Science CubeSat technology demonstration mission. The spacecraft was completed in about 2.5 years starting April 2014 through launch provider delivery in December of 2016. The mission was jointly funded by NASA’s Earth Science Technology Office, after competitive selection, and by NASA’s Earth Science Directorate. IceCube began its technology demonstration mission in June 2017, providing a pathway to advancing the understanding of ice clouds and their role in climate models; quite a tall order for a tiny spacecraft

NASA IceCube: CubeSat Demonstration of a Commercial 883-GHz Cloud Radiometer

On April 18 2017, NASA Goddard Space Flight Center's IceCube 3U CubeSat was launched by an ATLAS V rocket from Cape Canaveral Air Force Station on board a Cygnus resupply spacecraft, as part of NASA's CubeSat Launch Initiative. Onboard IceCube was an 883 GHz radiometer tuned to detecting ice content in clouds, marking the first time such frequency was used from low-Earth orbit. IceCube successfully demonstrated retrieval of ice water path, generating the first ever global cloud ice map at 883 GHz. Its success provides valuable lessons on how to approach a severely resource-limited space mission and provides great insight into how this experience can be applied to future high-risk, "non-class" missions for NASA and others. IceCube marks the first official NASA Earth Science CubeSat technology demonstration mission. The spacecraft was completed in about 2.5 years starting April 2014 through launch provider delivery in December of 2016. The mission was jointly funded by NASA's Earth Science Technology Office, after competitive selection, and by NASA's Earth Science Directorate. IceCube began its technology demonstration mission in June 2017, providing a pathway to advancing the understanding of ice clouds and their role in climate models; quite a tall order for a tiny spacecraft

Deep Space Network information system architecture study

The purpose of this article is to describe an architecture for the Deep Space Network (DSN) information system in the years 2000-2010 and to provide guidelines for its evolution during the 1990s. The study scope is defined to be from the front-end areas at the antennas to the end users (spacecraft teams, principal investigators, archival storage systems, and non-NASA partners). The architectural vision provides guidance for major DSN implementation efforts during the next decade. A strong motivation for the study is an expected dramatic improvement in information-systems technologies, such as the following: computer processing, automation technology (including knowledge-based systems), networking and data transport, software and hardware engineering, and human-interface technology. The proposed Ground Information System has the following major features: unified architecture from the front-end area to the end user; open-systems standards to achieve interoperability; DSN production of level 0 data; delivery of level 0 data from the Deep Space Communications Complex, if desired; dedicated telemetry processors for each receiver; security against unauthorized access and errors; and highly automated monitor and control

On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce tolerance against possible faults in an integrated circuit. This thesis studies and presents fault tolerance methods for network-onchip (NoC) which is a design paradigm targeted for very large systems-onchip. In a NoC resources, such as processors and memories, are connected to a communication network; comparable to the Internet. Fault tolerance in such a system can be achieved at many abstraction levels. The thesis studies the origin of faults in modern technologies and explains the classification to transient, intermittent and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Networks-on-chip are approached by exploring their main design choices: the selection of a topology, routing protocol, and flow control method. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model. The data link layer provides a reliable communication link over a physical channel. Error control coding is an efficient fault tolerance method especially against transient faults at this abstraction level. Error control coding methods suitable for on-chip communication are studied and their implementations presented. Error control coding loses its effectiveness in the presence of intermittent and permanent faults. Therefore, other solutions against them are presented. The introduction of spare wires and split transmissions are shown to provide good tolerance against intermittent and permanent errors and their combination to error control coding is illustrated. At the network layer positioned above the data link layer, fault tolerance can be achieved with the design of fault tolerant network topologies and routing algorithms. Both of these approaches are presented in the thesis together with realizations in the both categories. The thesis concludes that an optimal fault tolerance solution contains carefully co-designed elements from different abstraction levelsSiirretty Doriast

Intelligent LED Display

The goal of this project is to increase the overall redundancy, and ease-of-use during installation and operation, of large-format LED video displays for the professional touring and outdoor display industry. Using design concepts found in large-scale redundant networks, the system dynamically scales video output to the LED display and provides adaptive real-time fault detection and failover behaviors to ensure reliability in rigorous outdoor environments. This ultimately simplifies installation of a system, eliminating the need for the individual addressing of panels and alignment of video content. The designed system is inherently redundant and the ability to sustain failure of its components increases with the size of the display making it ideal for live applications

Análisis de desempeño de leach variando el porcentaje de cluster head

The LEACH protocol is a “standard” protocol used in the analysis and simulation of wireless sensor networks. This article analyzes the effect of varying parameter values in the LEACH protocol. In particular, the case of varying cluster head node assignments to , , and  of the total nodes of the network. Specifically, it shows the energy effect of this variation and the corresponding data traffic analysis, showing simulation results that illustrate the behavior resulting from this variation by using an approach of time-division multiplexing on the clusters.El protocolo LEACH es un protocolo “patrón” utilizado en análisis y simulación de redes de sensores inalámbricos. En este artículo, se analiza el efecto de variar los valores de los parámetros utilizados en el protocolo LEACH que, para el caso particular, se presenta la variación de asignación de nodos Cluster Head en porcentajes del ,  y  del total de los nodos de la red. En particular, se muestra el efecto energético de esta variación y su respectivo análisis de tráfico de datos, presentando resultados de simulación que ilustran el comportamiento de esta variación, bajo un enfoque de acceso múltiple por división de tiempo sobre los cluster encontrados por LEACH

MapMyVTA

Transportation is a very important part of our day-to-day life. Generally, it includes use of public transportation services like those provided by Valley Transportation Authority (VTA) to Santa Clara County. VTA has reported total combined boarding of light rails and buses as more than a million on yearly basis. This fact clearly indicates the importance of public transportation in a society. Obviously trip planning and schedule matching are two very decisive factors to improve transit experiences. Information related to services makes it easy for users to plan their journey ahead. Still manual planning and information discovery is time consuming, tedious, and prone to human errors. Therefore need of a better, user-friendly transit information system has been long felt. MapMyVTA is a web application that provides detailed information about VTA services to its users. MapMyVTA keeps the users updated about the timings of the buses, positions of the buses at a given time, and expected time of arrival of a bus at a given stop in a route. These features help users to match their timings with expected timings of the buses at the stop, to see their options about the number of buses en-route, to look up their connecting lines by a simple click at the connecting stops, and to plan their journey quickly with all system supported routes. Additional features, such as stop locator is useful to find more information about a particular stop with a near around attractions list with addresses, and view lines information feature make it easy to view a very detailed information about the bus lines

Self-Checking Ripple-Carry Adder with Ambipolar Silicon Nanowire FET

For the rapid adoption of new and aggressive technologies such as ambipolar Silicon NanoWire (SiNW), addressing fault-tolerance is necessary. Traditionally, transient fault detection implies large hardware overhead or performance decrease compared to permanent fault detection. In this paper, we focus on on-line testing and its application to ambipolar SiNW. We demonstrate on self - checking ripple - carry adder how ambipolar design style can help reduce the hardware overhead. When compared with equivalent CMOS process, ambipolar SiNW design shows a reduction in area of at least 56% (28%) with a decreased delay of 62% (6%) for Static (Transmission Gate) design style