56 research outputs found
Lower bounds for the depth of modular squaring
The modular squaring operation has attracted significant attention due to its potential in constructing cryptographic time-lock puzzles and verifiable delay functions. In such applications, it is important to understand precisely how quickly a modular squaring operation can be computed, even in parallel on dedicated hardware. We use tools from circuit complexity and number theory to prove concrete numerical lower bounds for squaring on a parallel machine, yielding nontrivial results for practical input bitlengths. For example, for , we prove that every logic circuit (over AND, OR, NAND, NOR gates of fan-in two) computing modular squaring on all -bit inputs (and any modulus that is at least ) requires depth (critical path length) at least 12. By a careful analysis of certain exponential Gauss sums related to the low-order bit of modular squaring, we also extend our results to the average case. For example, our results imply that every logic circuit (over any fan-in two basis) computing modular squaring on at least 76% of all 2048-bit inputs (for any RSA modulus that is at least ) requires depth at least 9
On The Parallelization Of Integer Polynomial Multiplication
With the advent of hardware accelerator technologies, multi-core processors and GPUs, much effort for taking advantage of those architectures by designing parallel algorithms has been made. To achieve this goal, one needs to consider both algebraic complexity and parallelism, plus making efficient use of memory traffic, cache, and reducing overheads in the implementations.
Polynomial multiplication is at the core of many algorithms in symbolic computation such as real root isolation which will be our main application for now.
In this thesis, we first investigate the multiplication of dense univariate polynomials with integer coefficients targeting multi-core processors. Some of the proposed methods are based on well-known serial classical algorithms, whereas a novel algorithm is designed to make efficient use of the targeted hardware. Experimentation confirms our theoretical analysis.
Second, we report on the first implementation of subproduct tree techniques on many-core architectures. These techniques are basically another application of polynomial multiplication, but over a prime field. This technique is used in multi-point evaluation and interpolation of polynomials with coefficients over a prime field
Models for Parallel Computation in Multi-Core, Heterogeneous, and Ultra Wide-Word Architectures
Multi-core processors have become the dominant processor architecture with 2, 4, and 8 cores on a chip being widely available and an increasing number of cores predicted for the future. In addition, the decreasing costs and increasing programmability of Graphic Processing Units (GPUs) have made these an accessible source of parallel processing power in general purpose computing. Among the many research challenges that this scenario has raised are the fundamental problems related to theoretical modeling of computation in these architectures. In this thesis we study several aspects of computation in modern parallel architectures, from modeling of computation in multi-cores and heterogeneous platforms, to multi-core cache management strategies, through the proposal of an architecture that exploits bit-parallelism on thousands of bits.
Observing that in practice multi-cores have a small number of cores, we propose a model for low-degree parallelism for these architectures. We argue that assuming a small number of processors (logarithmic in a problem's input size) simplifies the design of parallel algorithms. We show that in this model a large class of divide-and-conquer and dynamic programming algorithms can be parallelized with simple modifications to sequential programs, while achieving optimal parallel speedups. We further explore low-degree-parallelism in computation, providing evidence of fundamental differences in practice and theory between systems with a sublinear and linear number of processors, and suggesting a sharp theoretical gap between the classes of problems that are efficiently parallelizable in each case.
Efficient strategies to manage shared caches play a crucial role in multi-core performance. We propose a model for paging in multi-core shared caches, which extends classical paging to a setting in which several threads share the cache. We show that in this setting traditional cache management policies perform poorly, and that any effective strategy must partition the cache among threads, with a partition that adapts dynamically to the demands of each thread. Inspired by the shared cache setting,
we introduce the minimum cache usage problem, an extension to classical sequential paging in which algorithms must account for the amount of cache they use.
This cache-aware model seeks algorithms with good performance in terms of faults and the amount of cache used, and has applications in energy efficient caching and in shared cache scenarios.
The wide availability of GPUs has added to the parallel power of multi-cores, however, most applications underutilize the available resources. We propose a model for hybrid computation in heterogeneous systems with multi-cores and GPU, and describe strategies for generic parallelization and efficient scheduling of a large class of divide-and-conquer algorithms.
Lastly, we introduce the Ultra-Wide Word architecture and model, an extension of the word-RAM model, that allows for constant time operations on thousands of bits in parallel. We show that a large class of existing algorithms can be
implemented in the Ultra-Wide Word model, achieving speedups comparable to those of multi-threaded computations, while avoiding the more difficult aspects of parallel programming
A methodology for passenger-centred rail network optimisation
Optimising the allocation of limited resources, be they existing assets or
investment, is an ongoing challenge for rail network managers. Recently,
methodologies have been developed for optimising the timetable from the
passenger perspective. However, there is a gap for a decision support tool
which optimises rail networks for maximum passenger satisfaction, captures
the experience of individual passengers and can be adapted to different
networks and challenges. Towards building such a tool, this thesis develops a
novel methodology referred to as the Sheffield University Passenger Rail
Experience Maximiser (SUPREME) framework. First, a network assessment
metric is developed which captures the multi-stage nature of individual
passenger journeys as well as the effect of crowding upon passenger
satisfaction. Second, an agent-based simulation is developed to capture
individual passenger journeys in enough detail for the network assessment
metric to be calculated. Third, for the optimisation algorithm within SUPREME,
the Bayesian Optimisation method is selected following an experimental
investigation which indicates that it is well suited for ‘expensive-to-compute’
objective functions, such as the one found in SUPREME. Finally, in case studies
that include optimising the value engineering strategy of the proposed UK High
Speed Two network when saving £5 billion initial investment costs, the
SUPREME framework is found to improve network performance by the order
of 10%. This thesis shows that the SUPREME framework can find ‘good’
resource allocations for a ‘reasonable’ computational cost, and is sufficiently
adaptable for application to many rail network challenges. This indicates that a
decision support tool developed on the SUPREME framework could be widely
applied by network managers to improve passenger experience and increase
ticket revenue. Novel contributions made by this thesis are: the SUPREME
methodology, an international comparison between the Journey Time Metric
and Disutility Metric, and the application of the Bayesian Optimisation method
for maximising the performance of a rail network
Preliminary design study. Shuttle modular scanning spectroradiometer
Fundamental concepts on which to base a detailed design for a Shuttle Modular Scanning Spectroradiometer were developed, and a preliminary design is presented. The recommended design features modularity and flexibility. It includes a 75-cm f/1.7-telescope assembly in an all-reflective Schmidt configuration, a solid state scan system (pushbroom) with high resolution over a 15 deg field of view, and ten detector channels covering the spectral range from 0.45 to 12.5 micrometers. It uses charge transfer device techniques to accommodate a large number of detector elements for earth observation measurements. Methods for in-flight radiometric calibration, for image motion compensation, and for data processing are described. Recommendations for ground support equipment are included, and interfaces with the shuttle orbiter vehicle are illustrated
Coordinated budget allocation in multi-district highway agencies
Ph.DDOCTOR OF PHILOSOPH
Technology transfer: Transportation
The application of NASA derived technology in solving problems related to highways, railroads, and other rapid systems is described. Additional areas/are identified where space technology may be utilized to meet requirements related to waterways, law enforcement agencies, and the trucking and recreational vehicle industries
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