Strategies towards high performance (high-resolution/linearity) time-to-digital converters on field-programmable gate arrays

Time-correlated single-photon counting (TCSPC) technology has become popular in scientific research and industrial applications, such as high-energy physics, bio-sensing, non-invasion health monitoring, and 3D imaging. Because of the increasing demand for high-precision time measurements, time-to-digital converters (TDCs) have attracted attention since the 1970s. As a fully digital solution, TDCs are portable and have great potential for multichannel applications compared to bulky and expensive time-to-amplitude converters (TACs). A TDC can be implemented in ASIC and FPGA devices. Due to the low cost, flexibility, and short development cycle, FPGA-TDCs have become promising. Starting with a literature review, three original FPGA-TDCs with outstanding performance are introduced. The first design is the first efficient wave union (WU) based TDC implemented in Xilinx UltraScale (20 nm) FPGAs with a bubble-free sub-TDL structure. Combining with other existing methods, the resolution is further enhanced to 1.23 ps. The second TDC has been designed for LiDAR applications, especially in driver-less vehicles. Using the proposed new calibration method, the resolution is adjustable (50, 80, and 100 ps), and the linearity is exceptionally high (INL pk-pk and INL pk-pk are lower than 0.05 LSB). Meanwhile, a software tool has been open-sourced with a graphic user interface (GUI) to predict TDCs’ performance. In the third TDC, an onboard automatic calibration (AC) function has been realized by exploiting Xilinx ZYNQ SoC architectures. The test results show the robustness of the proposed method. Without the manual calibration, the AC function enables FPGA-TDCs to be applied in commercial products where mass production is required.Time-correlated single-photon counting (TCSPC) technology has become popular in scientific research and industrial applications, such as high-energy physics, bio-sensing, non-invasion health monitoring, and 3D imaging. Because of the increasing demand for high-precision time measurements, time-to-digital converters (TDCs) have attracted attention since the 1970s. As a fully digital solution, TDCs are portable and have great potential for multichannel applications compared to bulky and expensive time-to-amplitude converters (TACs). A TDC can be implemented in ASIC and FPGA devices. Due to the low cost, flexibility, and short development cycle, FPGA-TDCs have become promising. Starting with a literature review, three original FPGA-TDCs with outstanding performance are introduced. The first design is the first efficient wave union (WU) based TDC implemented in Xilinx UltraScale (20 nm) FPGAs with a bubble-free sub-TDL structure. Combining with other existing methods, the resolution is further enhanced to 1.23 ps. The second TDC has been designed for LiDAR applications, especially in driver-less vehicles. Using the proposed new calibration method, the resolution is adjustable (50, 80, and 100 ps), and the linearity is exceptionally high (INL pk-pk and INL pk-pk are lower than 0.05 LSB). Meanwhile, a software tool has been open-sourced with a graphic user interface (GUI) to predict TDCs’ performance. In the third TDC, an onboard automatic calibration (AC) function has been realized by exploiting Xilinx ZYNQ SoC architectures. The test results show the robustness of the proposed method. Without the manual calibration, the AC function enables FPGA-TDCs to be applied in commercial products where mass production is required

Efficient proofs of software exploitability for real-world processors

CRAhttps://eprint.iacr.org/2022/1223.pdfPublished versio

Measurements, Models, Systems and Design

531 s.

Analysis of H/W & S/W techniques for data reduction in high speed digital image processing

With the widespread utilization of charge-coupled-devices, there is much interest in methods to efficiently process images. The processing, manipulation, and storage of photographic quality digital images place significant demands on today\u27s computers. Even with today\u27s high performance bus structure and real-time operating systems, manipulating full resolution image data may quickly overwhelm computer hardware and software. In response to this, data reduction techniques have been developed to aid in resolving this problem. Two common data reduction techniques include data sub-sampling and data averaging. Data sub-sampling approach is simplistic in nature and perhaps easiest to implement in both hardware and/or software. This approach involves sub-sampling the full resolution image data to a lower resolution. Selection of sub-sampled element of the full resolution image is random in nature. This random selection makes sub-sampling an effective technique for flat image fields but degrades or softens the image for edges information quality/content. Data averaging approach is more difficult and complex to implement in both hardware and software than the sub-sampling approach. The data averaging approach involves a two dimensional averaging function to sub-sample the full resolution image data to a lower resolution. Averaging area parameters may be chosen to average X consecutive pixels, and Y consecutive lines. Although more complex, data averaging more effectively retains edge information. This thesis investigates the two-dimensional, pixel data-averaging method for data reduction. It supports the use of a pixel-averaging algorithm in conjunction with, or independent from compression techniques which may be employed elsewhere within the same system. Hardware and software implementations are presented to solve this system problem. The hardware architecture design is based on a pixel averaging application specific integrated circuit. Software routines written in C programming language are presented to perform this data-averaging task. Performance comparisons are made between the hardware and software implementations for image resolutions up to 2048 by 3072 pixels, and under several averaging conditions. This thesis also provides a survey of various types of charge-coupled devices sensors, focusing on their abilities and limitations for data averaging. It presents several applications where this type of data reduction would be advantageous

Performance-Driven Energy-Efficient VLSI.

Today, there are two prevalent platforms in VLSI systems: high-performance and ultra-low power. High-speed designs, usually operating at GHz level, provide the required computation abilities to systems but also consume a large amount of power; microprocessors and signal processing units are examples of this type of designs. For ultra-low power designs, voltage scaling methods are usually used to reduce power consumption and extend battery life. However, circuit delay in ultra-low power designs increases exponentially, as voltage is scaled below Vth, and subthreshold leakage energy also increases in a near-exponential fashion. Many methods have been proposed to address key design challenges on these two platforms, energy consumption in high-performance designs, and performance/reliability in ultra-low power designs. In this thesis, charge-recovery design is explored as a solution targeting both platforms to achieve increased energy efficiency over conventional CMOS designs without compromising performance or reliability. To improve performance while still achieving high energy efficiency for ultra-low power designs, we propose Subthreshold Boost Logic (SBL), a new circuit family that relies on charge-recovery design techniques to achieve order-of-magnitude improvements in operating frequencies, and achieve high energy efficiency compared to conventional subthreshold designs. To demonstrate the performance and energy efficiency of SBL, we present a 14-tap 8-bit finite-impulse response (FIR) filter test-chip fabricated in a 0.13µm process. With a single 0.27V supply, the test-chip achieves its most energy efficient operating point at 20MHz, consuming 15.57pJ per cycle with a recovery rate of 89% and a FoM equal to 17.37 nW/Tap/MHz/InBit/CoeffBit. To reduce energy consumption at multi-GHz level frequencies, we explore the application of resonant-clocking to the design of a 5-bit non-interleaved resonant-clock ash ADC with a sampling rate of 7GS/s. The ADC has been designed in a 65nm bulk CMOS process. An integrated 0.77nH inductor is used to resonate the entire clock distribution network to achieve energy efficient operation. Operating at 5.5GHz, the ADC consumes 28mW, yielding 396fJ per conversion step. The clock network accounts for 10.7% of total power and consumes 54% less energy over CV^2. By comparison, in a typical ash ADC design, 30% of total power is clock-related.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/89779/1/wsma_1.pd

Exploration and Design of Power-Efficient Networked Many-Core Systems

Multiprocessing is a promising solution to meet the requirements of near future applications. To get full benefit from parallel processing, a manycore system needs efficient, on-chip communication architecture. Networkon- Chip (NoC) is a general purpose communication concept that offers highthroughput, reduced power consumption, and keeps complexity in check by a regular composition of basic building blocks. This thesis presents power efficient communication approaches for networked many-core systems. We address a range of issues being important for designing power-efficient manycore systems at two different levels: the network-level and the router-level. From the network-level point of view, exploiting state-of-the-art concepts such as Globally Asynchronous Locally Synchronous (GALS), Voltage/ Frequency Island (VFI), and 3D Networks-on-Chip approaches may be a solution to the excessive power consumption demanded by today’s and future many-core systems. To this end, a low-cost 3D NoC architecture, based on high-speed GALS-based vertical channels, is proposed to mitigate high peak temperatures, power densities, and area footprints of vertical interconnects in 3D ICs. To further exploit the beneficial feature of a negligible inter-layer distance of 3D ICs, we propose a novel hybridization scheme for inter-layer communication. In addition, an efficient adaptive routing algorithm is presented which enables congestion-aware and reliable communication for the hybridized NoC architecture. An integrated monitoring and management platform on top of this architecture is also developed in order to implement more scalable power optimization techniques. From the router-level perspective, four design styles for implementing power-efficient reconfigurable interfaces in VFI-based NoC systems are proposed. To enhance the utilization of virtual channel buffers and to manage their power consumption, a partial virtual channel sharing method for NoC routers is devised and implemented. Extensive experiments with synthetic and real benchmarks show significant power savings and mitigated hotspots with similar performance compared to latest NoC architectures. The thesis concludes that careful codesigned elements from different network levels enable considerable power savings for many-core systems.Siirretty Doriast

Ultrasound power measurement system design using PVDF sensor and FPGA technology

Ultrasound machine is widely used in industrial and medical institutions. With the purpose of avoiding the unwanted power exposed on human, ultrasound power meter is employed to measure output power of ultrasound machine for diagnostic, therapeutic and non-destructive testing purposes. The existing ultrasound power meter, however, is high-cost, low-resolution and only for specific machine. Radiation balance method consists of calculation and calibration complexity while the calorimetric produces inaccurate result compared to the standard. On the other hand, application of piezoelectric sensor in hydrophone-based measurement requires advancement on processing device and technique. This work deals with the development of ultrasound power measurement system on Field Programmable Gate Array (FPGA) platform. Polyvinylidene Fluoride (PVDF) was employed to sense medical ultrasonic signal. PVDF film’s behavior and its electro-acoustic model were observed. Signal conditioner circuit was then described. Next, a robust low-cost casing for PVDF sensor was built, followed by the proposal of the use of digital-system ultrasound processing algorithm. The simulated sensor provided 2.5 MHz to 8.5 MHz response with output amplitude of around 4 Vpp. Ultrasound analog circuits, after filtering and amplifying, provided frequency range from 1 MHz until 10 MHz with -5 V to +5 V voltage head-rooms to offer a wideband medical ultrasonic acceptance. Frequency from 500 kHz to 10 MHz with temperature span from 10 oC to 50 oC and power range from 1 mW/cm2 up to 10 W/cm2 (with resolution 0.05 mW/cm2) had been expected by using the established hardware. The test result shows that the platform is able to process 10 us ultrasound data with 20 ns time-domain resolution and 0.4884 mVpp magnitude resolutions. This waveform was then displayed in the personal computer’s (PCs) graphical user interface (GUI) and the calculation result was displayed on liquid crystal display (LCD) via microcontroller. The whole system represents a novel design of low-cost ultrasound power measurement system with high-precision capability for medical application. This may improve the existing power meters which have intensity resolution limitation (at best combination, of all products, utilize: 0.25 MHz - 10 MHz frequency coverage; 10 oC to 30 oC working temperature; 0 W/cm2 - 30 W/cm2 power range; 20 mW/cm2 resolution), neither having mechanism to handle the temperature disturbance nor possibility for further data analysis