4,129 research outputs found
DFT and BIST of a multichip module for high-energy physics experiments
Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie
Narrow bandwidth video Patent
Improvements in receiver of narrow bandwidth television syste
Design and Test Space Exploration of Transport-Triggered Architectures
This paper describes a new approach in the high level design and test of transport-triggered architectures (TTA), a special type of application specific instruction processors (ASIP). The proposed method introduces the test as an additional constraint, besides throughput and circuit area. The method, that calculates the testability of the system, helps the designer to assess the obtained architectures with respect to test, area and throughput in the early phase of the design and selects the most suitable one. In order to create the templated TTA, the ÂżMOVEÂż framework has been addressed. The approach is validated with respect to the ÂżCryptÂż Unix applicatio
Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits
Power dissipation in sequential circuits is due to increased toggling count
of Circuit under Test, which depends upon test vectors applied. If successive
test vectors sequences have more toggling nature then it is sure that toggling
rate of flip flops is higher. Higher toggling for flip flops results more power
dissipation. To overcome this problem, one method is to use GA to have test
vectors of high fault coverage in short interval, followed by Hamming distance
management on test patterns. This approach is time consuming and needs more
efforts. Another method which is purposed in this paper is a PSO based Frame
Work to optimize power dissipation. Here target is to set the entire test
vector in a frame for time period 'T', so that the frame consists of all those
vectors strings which not only provide high fault coverage but also arrange
vectors in frame to produce minimum toggling
Advanced analog television study final report, 4 nov. - 19 dec. 1963
Information bandwidth reduction for analog television signals - Description of multiple interlace syste
E-QED: Electrical Bug Localization During Post-Silicon Validation Enabled by Quick Error Detection and Formal Methods
During post-silicon validation, manufactured integrated circuits are
extensively tested in actual system environments to detect design bugs. Bug
localization involves identification of a bug trace (a sequence of inputs that
activates and detects the bug) and a hardware design block where the bug is
located. Existing bug localization practices during post-silicon validation are
mostly manual and ad hoc, and, hence, extremely expensive and time consuming.
This is particularly true for subtle electrical bugs caused by unexpected
interactions between a design and its electrical state. We present E-QED, a new
approach that automatically localizes electrical bugs during post-silicon
validation. Our results on the OpenSPARC T2, an open-source
500-million-transistor multicore chip design, demonstrate the effectiveness and
practicality of E-QED: starting with a failed post-silicon test, in a few hours
(9 hours on average) we can automatically narrow the location of the bug to
(the fan-in logic cone of) a handful of candidate flip-flops (18 flip-flops on
average for a design with ~ 1 Million flip-flops) and also obtain the
corresponding bug trace. The area impact of E-QED is ~2.5%. In contrast,
deter-mining this same information might take weeks (or even months) of mostly
manual work using traditional approaches
Flip Flops Design in Quantum Dot Cellular Automata Technology: Towards Digitization
Quantum-Dot Cellular Automata (QCA) is a transistor-less technology. In QCA, Columbic repulsion between electrons in the quantum dots makes data transfer possible. This paper presents the design of flip flops using a proposed Rotated-Normal Cells with Displacement (RND) inverter and a cell interaction method. The SR latch, SR Flip Flop (FF), D FF, and T FF are developed using QCA. The proposed D FF gives total and average energy dissipation of 1.31e-002eV and 1.19e-003eV respectively. It also gives a delay of 1 clock phase. The Proposed T FF provides total and average energy dissipation of 2.40e-002eV and 2.18e-003eV respectively, depicting efficient D FF and T FF in energy dissipation. The proposed SR Flip flop design gives an efficient area. The FFs with the proposed RND inverter and cell interaction method can be the best choice for future Nano communication to construct Nano circuits with less energy dissipation and high speed
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