Integration of energy storage components with cascaded H-bridge multilevel converters

In recent years, multilevel converters have gained considerable attention in medium-voltage motor drive and grid applications. This popularity is owed to their reduced voltage stress on the semiconductor devices used in their structure. In addition, multilevel converters generate near sinusoidal outputs with low harmonic distortions. Other advantages of such converters include inherent modularity and low dv/dt stresses. In general, multilevel power electronic converters are classified into three main topologies: diode-clamped, flying-capacitor, and cascaded H-bridge. A cascaded H-bridge multilevel converter is created when several H-bridge cells are placed in series. Each H-bridge cell must be fed by a stiff voltage source. In earlier implementations, every one of these voltage sources had to contribute to the overall power supplied to the load. Later, it was demonstrated that under certain operating conditions, one can replace all but one of these sources with energy storage devices, e.g., capacitors. In other words, the entire power can be supplied by only one source. The replacing capacitors must only maintain a constant dc voltage supplying zero net power. Although this approach benefits from cost reductions, balancing the voltages across the replacing capacitors turns out to be a challenge. In this thesis, the operating conditions under which the capacitor voltage regulation is feasible are first analytically investigated. The results show that the amplitude of the output voltage as well as the power factor of the load current determines the regulation range when the staircase modulation method is employed. In order to extend the regulation range for the replacing capacitors, a new control scheme - phase shift modulation - is proposed. This method is more robust when compared to existing methods. In this method, the main H-bridge cell of the multilevel converter operates at the fundamental frequency and the auxiliary cells run at the PWM frequency. Finally, the sigma-delta modulation method has been utilized to extend the capacitor voltage regulation range. This method benefits from simplicity in implementation in comparison to PWM techniques. The analytical and simulation results prove the effectiveness of the proposed approaches. They are also consistent with the results of the experiment --Abstract, page iv

Methods and Devices for Modifying Active Paths in a K-Delta-1-Sigma Modulator

The invention relates to an improved K-Delta-1-Sigma Modulators (KG1Ss) that achieve multi GHz sampling rates with 90 nm and 45 nm CMOS processes, and that provide the capability to balance performance with power in many applications. The improved KD1Ss activate all paths when high performance is needed (e.g. high bandwidth), and reduce the effective bandwidth by shutting down multiple paths when low performance is required. The improved KD1Ss can adjust the baseband filtering for lower bandwidth, and can provide large savings in power consumption while maintaining the communication link, which is a great advantage in space communications. The improved KD1Ss herein provides a receiver that adjusts to accommodate a higher rate when a packet is received at a low bandwidth, and at a initial lower rate, power is saved by turning off paths in the KD1S Analog to Digital Converter, and where when a higher rate is required, multiple paths are enabled in the KD1S to accommodate the higher band widths

Design Considerations for Multistandard Cascade ΣΔ Modulators

This paper discusses design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multistandard wireless receivers. Four different standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain behavioural simulations considering a 0.13μm CMOS implementation are shown to validate the presented approach.Ministerio de Educación y Ciencia TEC2004-01752/MI

Design Considerations for Multistandard Cascade ΣΔ Modulators

This paper discusses design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multistandard wireless receivers. Four different standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain behavioural simulations considering a 0.13μm CMOS implementation are shown to validate the presented approach.This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2004-01752/MIC.Peer reviewe

Design techniques for sigma-delta modulators in communications applications

Specialised design techniques for sigma-delta modulators are described in this thesis with all of the examples coming from modern communications systems. The noise shaping and the signal transfer functions can be optimised using a weighted least squares approach. Numerical problems arising in the optimisation as a result of high oversampling rates are overcome through the use a simple transformation. The application to digitising audio is discussed, with the conclusion that Butterworth response noise shaping is preferable to inverse Chebyshev noise shaping for audio applications. An example of optimising the signal transfer function to provide immunity to instability brought about by large out-of-band signals is also presented. The use of redundant arithmetic in the implementation of very high speed sigma-delta modulators is introduced, together with a DAC / filter combination suitable for reconstructing an analogue signal from the redundant arithmetic SDM. An improved topology for a speech compander is described which offers a number of significant advantages over existing published methods. This uses no external components for ac coupling or setting the response time-constant, yet is robust and insensitive to parasitic components and process variations. This has been integrated on a CMOS IC process and the results are compared with the high level simulations. A simulation method which allows the verification of switched-capacitor schematics with several orders of magnitude speed improvements over commercially available simulation tools is discussed. The method assumes ideal components, with internally controllable switches and reduces the schematic netlist to the few key equations that an experienced designer would derive manually. This process is fully automated and consequently is useful for providing confidence in implementations of complex SC systems

Oversampling PCM techniques and optimum noise shapers for quantizing a class of nonbandlimited signals

We consider the efficient quantization of a class of nonbandlimited signals, namely, the class of discrete-time signals that can be recovered from their decimated version. The signals are modeled as the output of a single FIR interpolation filter (single band model) or, more generally, as the sum of the outputs of L FIR interpolation filters (multiband model). These nonbandlimited signals are oversampled, and it is therefore reasonable to expect that we can reap the same benefits of well-known efficient A/D techniques that apply only to bandlimited signals. We first show that we can obtain a great reduction in the quantization noise variance due to the oversampled nature of the signals. We can achieve a substantial decrease in bit rate by appropriately decimating the signals and then quantizing them. To further increase the effective quantizer resolution, noise shaping is introduced by optimizing prefilters and postfilters around the quantizer. We start with a scalar time-invariant quantizer and study two important cases of linear time invariant (LTI) filters, namely, the case where the postfilter is the inverse of the prefilter and the more general case where the postfilter is independent from the prefilter. Closed form expressions for the optimum filters and average minimum mean square error are derived in each case for both the single band and multiband models. The class of noise shaping filters and quantizers is then enlarged to include linear periodically time varying (LPTV)M filters and periodically time-varying quantizers of period M. We study two special cases in great detail

Components for oversampled signal processors

Oversampled converters trade transmission bandwidth for resolution. An idealized model gives an insight into the way in which signals are encoded and thus how they can be manipulated. Oversampling offers a form of signal processing that requires simple processing elements capable of exploiting the growing clock speeds available in integrated solutions. Simultaneously avoids the need for analog circuitry. This paper reviews common operations that can be performed on oversampled signals