Low Voltage Low Power Analogue Circuits Design

Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the non–conventional ones which are bulk–driven (BD), floating–gate (FG), quasi–floating–gate (QFG), bulk–driven floating–gate (BD–FG) and bulk–driven quasi–floating–gate (BD–QFG) techniques. The thesis also looks at ways of implementing structures of well–known and modern active elements operating in voltage–, current–, and mixed–mode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fully–differential second generation current conveyor (FB–CCII), fully–balanced differential difference amplifier (FB–DDA), voltage differencing transconductance amplifier (VDTA), current–controlled current differencing buffered amplifier (CC–CDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diode–less rectifier and inductance simulations, as well as low–pass, band–pass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.

High gain and bandwidth current-mode amplifiers : study and implementation

Doutoramento em Engenharia ElectrotécnicaEsta tese aborda o problema do projecto de amplificadores com grandes produtos de ganho por largura de banda. A aplicação final considerada consistiu no projecto de amplificadores adequados à recepção de sinais ópticos em sistemas de transmissão ópticos usando o espaço livre. Neste tipo de sistemas as maiores limitações de ganho e largura de banda surgem nos circuitos de entrada. O uso de detectores ópticos com grande área fotosensível é uma necessidade comum neste tipo de sistemas. Estes detectores apresentam grandes capacidades intrínsecas, o que em conjunto com a impedância de entrada apresentada pelo amplificador estabelece sérias restrições no produto do ganho pela largura de banda. As técnicas mais tradicionais para combater este problema recorrem ao uso de amplificadores com retroacção baseados em configurações de transimpedância. Estes amplificadores apresentam baixas impedâncias de entrada devido à acção da retroacção. Contudo, os amplificadores de transimpedância também apresentam uma relação directa entre o ganho e a impedância de entrada. Logo, diminuir a impedância de entrada implica diminuir o ganho. Esta tese propõe duas técnicas novas para combater os problemas referidos. A primeira técnica tem por base uma propriedade fundamental dos amplificadores com retroacção. Em geral, todos os circuitos electrónicos têm tempos de atraso associados, os amplificadores com retroacção não são uma excepção a esta regra. Os tempos de atraso são em geral reconhecidos como elementos instabilizadores neste tipos da amplificadores. Contudo, se usados judiciosamente, este tempos de atraso podem ser explorados como uma forma da aumentar a largura de banda em amplificadores com retroacção. Com base nestas ideias, esta tese apresenta o conceito geral de reatroacção com atraso, como um método de optimização de largura de banda em amplificadores com retroacção. O segundo método baseia-se na destruição da dualidade entre ganho e impedância de entrada existente nos amplificadores de transimpedância. O conceito de adaptação activa em modo de corrente é neste sentido uma forma adequada para separar o detector óptico da entrada do amplificador. De acordo com este conceito, emprega-se um elemento de adaptação em modo de corrente para isolar o detector óptico da entrada do amplificador. Desta forma as tradicionais limitações de ganho e largura de banda podem ser tratadas em separado. Esta tese defende o uso destas técnicas no desenho de amplificadores de transimpedância para sistemas de recepção de sinais ópticos em espaço livre.This thesis addresses the problem of achieving high gain-bandwidth products in amplifiers. The adopted framework consisted on the design of a free-space optical (FSO) front end amplifier able to amplify very small optical signals over large frequency bandwidths. The major gain-bandwidth limitations in FSO front end amplifiers arise due to the input circuitry. Usually, it is necessary to have large area optical detectors in order to maximize signal reception. These detectors have large intrinsic capacitances, which together with the amplifier input impedance poses a severe restriction on the gain-bandwidth product. Traditional techniques to combat this gain-bandwidth limitation resort to feedback amplifiers consisting on transimpedance configurations. These amplifiers have small input impedances due to the feedback action. Nevertheless, transimpedance amplifiers have a direct relation between gain and input impedance. Thus reducing the input impedance usually implies reducing the gain. This thesis advances two new methods suitable to combat the above mentioned problems. The first method is based on a fundamental property of feedback amplifiers. In general, all electronic circuits have associated time delays, and feedback amplifiers are not an exception to this rule. Time delays in feedback amplifiers have been recognized as destabilizing elements. Nevertheless, when used with appropriate care, these delays can be exploited as bandwidth enhancement elements. Based on these ideas, this thesis presents the general concept of delayed feedback, as a bandwidth optimization method suitable for feedback amplifiers. The second method is based on the idea of destroying the impedance-gain duality in transimpedance amplifiers. The concept of active current matching is in this sense a suitable method to detach the optical detector from the transimpedance amplifier input. According to this concept, a current matching device (CMD) is used to convey the signal current sensed by the optical detector, to the amplifier’s input. Using this concept the traditional gainbandwidth limitations can be treated in a separate fashion. This thesis advocates the usage of these techniques for the design of transimpedance amplifiers suited for FSO receiving systems

Novel techniques for the design and practical realization of switched-capacitor circuits in deep-submicron CMOS technologies

Dissertação apresentada para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores pela Universidade Nova de Lisboa, Faculdade de Ciências e TecnologiaSwitches presenting high linearity are more and more required in switched-capacitor circuits,namely in 12 to 16 bits resolution analog-to-digital converters. The CMOS technology evolves continuously towards lower supply voltages and, simultaneously, new design techniques are necessary to fulfill the realization of switches exhibiting a high dynamic range and a distortion compatible with referred resolutions. Moreover, with the continuously downing of the sizes, the physic constraints of the technology must be considered to avoid the excessive stress of the devices when relatively high voltages are applied to the gates. New switch-linearization techniques, with high reliability, must be necessarily developed and demonstrated in CMOS integrated circuits. Also, the research of new structures of circuits with switched-capacitor is permanent. Simplified and efficient structures are mandatory, adequate to the new demands emerging from the proliferation of portable equipments, necessarily with low energy consumption while assuring high performance and multiple functions. The work reported in this Thesis comprises these two areas. The behavior of the switches under these new constraints is analyzed, being a new and original solution proposed, in order to maintain the performance. Also, proposals for the application of simpler clock and control schemes are presented, and for the use of open-loop structures and amplifiers with localfeedback. The results, obtained in laboratory or by simulation, assess the feasibility of the presented proposals

Cryogenic Control Beyond 100 Qubits

Quantum computation has been a major focus of research in the past two decades, with recent experiments demonstrating basic algorithms on small numbers of qubits. A large-scale universal quantum computer would have a profound impact on science and technology, providing a solution to several problems intractable for classical computers. To realise such a machine, today's small experiments must be scaled up, and a system must be built which provides control and measurement of many hundreds of qubits. A device of this scale is challenging: qubits are highly sensitive to their environment, and sophisticated isolation techniques are required to preserve the qubits' fragile states. Solid-state qubits require deep-cryogenic cooling to suppress thermal excitations. Yet current state-of-the-art experiments use room-temperature electronics which are electrically connected to the qubits. This thesis investigates various scalable technologies and techniques which can be used to control quantum systems. With the requirements for semiconductor spin-qubits in mind, several custom electronic systems, to provide quantum control from deep cryogenic temperatures, are designed and measured. A system architecture is proposed for quantum control, providing a scalable approach to executing quantum algorithms on a large number of qubits. Control of a gallium arsenide qubit is demonstrated using a cryogenically operated FPGA driving custom gallium arsenide switches. The cryogenic performance of a commercial FPGA is measured, as the main logic processor in a cryogenic quantum control system, and digital-to-analog converters are analysed during cryogenic operation. Recent work towards a 100-qubit cryogenic control system is shown, including the design of interconnect solutions and multiplexing circuitry. With qubit fidelity over the fault-tolerant threshold for certain error correcting codes, accompanying control platforms will play a key role in the development of a scalable quantum machine

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Disseny microelectrnic de circuits discriminadors de polsos pel detector LHCb

The aim of this thesis is to present a solution for implementing the front end system of the Scintillator Pad Detector (SPD) of the calorimeter system of the LHCb experiment that will start in 2008 at the Large Hadron Collider (LHC) at CERN. The requirements of this specific system are discussed and an integrated solution is presented, both at system and circuit level. We also report some methodological achievements. In first place, a method to study the PSRR (and any transfer function) in fully differential circuits taking into account the effect of parameter mismatch is proposed. Concerning noise analysis, a method to study time variant circuits in the frequency domain is presented and justified. This would open the possibility to study the effect of 1/f noise in time variants circuits. In addition, it will be shown that the architecture developed for this system is a general solution for front ends in high luminosity experiments that must be operated with no dead time and must be robust against ballistic deficit

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Amplificador CMOS de baixo ruído para imagiologia médica

Mestrado em Engenharia Electrónica e TelecomunicaçõesA presente dissertação aborda o projecto de um frontend analógico integrado para sincronização e amplificação de sinais produzidos por um fotomultiplicador de silício. A solução proposta pretende possibilitar medidas de tempo com resoluções na ordem dos picosegundos, para implementação em equipamentos compactos dedicados à Tomografia por Emissão de Positrões, com capacidade para medida do tempo de voo de fotões (TOFPET). O canal de frontend completo foi implementado em tecnologia CMOS 130nm, e compreende blocos de préamplificação, integração de carga, equilíbrio dinâmico do ponto de operação, bem como circuitos geradores de correntes de referência, para uma área total em silício de 500x90 μm. A discussão de resultados é baseada em simulações póslayout, e as linhas de investigação futuras são propostas.An analogue CMOS frontend for triggering and amplification of signals produced by a silicon photomultiplier (SiPM) is proposed. The solution intends to achieve picosecond resolution timing measurements for compact timeofflight Positron Emission Tomography (TOFPET) medical imaging equipments. A 130nm technology was used to implement such frontend, and the design includes preamplification, shaping, baseline holder and biasing circuitry, for a total silicon area of 500x90 μm. Postlayout simulation results are discussed, and ways to optimize the design are proposed