3 research outputs found
Operating System Concepts for Reconfigurable Computing: Review and Survey
One of the key future challenges for reconfigurable computing is to enable higher design productivity and a more easy way to use reconfigurable computing systems for users that are unfamiliar with the underlying concepts. One way of doing this is to provide standardization and abstraction, usually supported and enforced by an operating system. This article gives historical review and a summary on ideas and key concepts to include reconfigurable computing aspects in operating systems. The article also presents an overview on published and available operating systems targeting the area of reconfigurable computing. The purpose of this article is to identify and summarize common patterns among those systems that can be seen as de facto standard. Furthermore, open problems, not covered by these already available systems, are identified
Validation and verification of the interconnection of hardware intellectual property blocks for FPGA-based packet processing systems
As networks become more versatile, the computational requirement for supporting additional
functionality increases. The increasing demands of these networks can be met by Field Programmable
Gate Arrays (FPGA), which are an increasingly popular technology for implementing packet processing
systems. The fine-grained parallelism and density of these devices can be exploited to meet the
computational requirements and implement complex systems on a single chip. However, the increasing
complexity of FPGA-based systems makes them susceptible to errors and difficult to test and debug.
To tackle the complexity of modern designs, system-level languages have been developed to provide
abstractions suited to the domain of the target system. Unfortunately, the lack of formality in
these languages can give rise to errors that are not caught until late in the design cycle. This
thesis presents three techniques for verifying and validating FPGA-based packet processing systems
described in a system-level description language. First, a type system is applied to the system
description language to detect errors before implementation. Second, system-level transaction
monitoring is used to observe high-level events on-chip following implementation. Third, the
high-level information embodied in the system description language is exploited to allow the system
to be automatically instrumented for on-chip monitoring.
This thesis demonstrates that these techniques catch errors which are undetected by traditional
verification and validation tools. The locations of faults are specified and errors are caught
earlier in the design flow, which saves time by reducing synthesis iterations
Parallel and Distributed Computing
The 14 chapters presented in this book cover a wide variety of representative works ranging from hardware design to application development. Particularly, the topics that are addressed are programmable and reconfigurable devices and systems, dependability of GPUs (General Purpose Units), network topologies, cache coherence protocols, resource allocation, scheduling algorithms, peertopeer networks, largescale network simulation, and parallel routines and algorithms. In this way, the articles included in this book constitute an excellent reference for engineers and researchers who have particular interests in each of these topics in parallel and distributed computing