Towards FPGA hardware in the loop for QCA simulation

As transistors begin to hit raw physical limits and performance barriers, other technologies are being researched to potentially replace conventional integrated circuit technology. Quantum-dot Cellular Automata (QCA) is one such technology which executes computations using coulomb interactions and quantum-mechanical effects. Part of this research is pursuant to the design of circuits which exploit QCA technology and take advantage of what it has to offer. These circuits must be simulated to ensure their functionality and help prove the viability of QCA. These simulations, like many scientific computing applications, can take a long time to complete; hours or days, depending on their size and complexity. Many scientific applications have benefitted from research into Field Programmable Gate Array (FPGA) application development, which has been used to accelerate the speed at which such simulations execute. This thesis investigates the possibility of using FPGAs to accelerate the simulation of QCA circuits. The hardware developed is a streaming type architecture using floating point arithmetic and hardware/software techniques. Hardware implementation shows the system to run slower than the existing software code, but demonstrates the ability to simulate a small QCA circuit. Analysis of the design reveals good potential for achieving speedup, and an alternate design is proposed to improve the execution time. In the course of this work, improvements to the existing software are also developed and contributed to the community