Precise Timing of Digital Signals: Circuits and Applications

With the rapid advances in process technologies, the performance of state-of-the-art integrated circuits is improving steadily. The drive for higher performance is accompanied with increased emphasis on meeting timing constraints not only at the design phase but during device operation as well. Fortunately, technology advancements allow for even more precise control of the timing of digital signals, an advantage which can be used to provide solutions that can address some of the emerging timing issues. In this thesis, circuit and architectural techniques for the precise timing of digital signals are explored. These techniques are demonstrated in applications addressing timing issues in modern digital systems. A methodology for slow-speed timing characterization of high-speed pipelined datapaths is proposed. The technique uses a clock-timing circuit to create shifted versions of a slow-speed clock. These clocks control the data flow in the pipeline in the test mode. Test results show that the design provides an average timing resolution of 52.9ps in 0.18μm CMOS technology. Results also demonstrate the ability of the technique to track the performance of high-speed pipelines at a reduced clock frequency and to test the clock-timing circuit itself. In order to achieve higher resolutions than that of an inverter/buffer stage, a differential (vernier) delay line is commonly used. To allow for the design of differential delay lines with programmable delays, a digitally-controlled delay-element is proposed. The delay element is monotonic and achieves a high degree of transfer characteristics' (digital code vs. delay) linearity. Using the proposed delay element, a sub-1ps resolution is demonstrated experimentally in 0.18μm CMOS. The proposed delay element with a fixed delay step of 2ps is used to design a high-precision all-digital phase aligner. High-precision phase alignment has many applications in modern digital systems such as high-speed memory controllers, clock-deskew buffers, and delay and phase-locked loops. The design is based on a differential delay line and a variation tolerant phase detector using redundancy. Experimental results show that the phase aligner's range is from -264ps to +247ps which corresponds to an average delay step of approximately 2.43ps. For various input phase difference values, test results show that the difference is reduced to less than 2ps at the output of the phase aligner. On-chip time measurement is another application that requires precise timing. It has applications in modern automatic test equipment and on-chip characterization of jitter and skew. In order to achieve small conversion time, a flash time-to-digital converter is proposed. Mismatch between the various delay comparators limits the time measurement precision. This is demonstrated through an experiment in which a 6-bit, 2.5ps resolution flash time-to-digital converter provides an effective resolution of only 4-bits. The converter achieves a maximum conversion rate of 1.25GSa/s

The post office experience: designing a large asynchronous chip

Journal ArticleThe Post Office is an asynchronous, 300,000 transistor, full-custom CMOS chip designed as the communication component for the Mayfly scalable parallel processor. Performance requirements led to the development of a design style which permits the design of sequential circuits operating under a restricted form of multiple input change sign alling called burst-mode. The Post Office complexity forced us to develop a set of design fools capable of correctly synthesizing transistor circuits front state machine and equation specifications, and capable of verifying the correctness of the resultant circuity using implementation specific timing assumptions. The paper provides a case study of this design experience

A Static Time Analysis of 1-bit to 32-page SCA architecture for Logic Test

This research proposes the Static Time Analysis  of  32  page  Single  cycle  access  (SCA)  architecture  for Logic test. The timing analysis of each and very path of Logic test are observed that is setup and hold timings are calculated.  It also eliminates the peak power consumption problem of conventional shift-based scan chains and reduces the activity during shift and capture cycles using Clock-Gating technique. This leads to more realistic circuit behavior during at-speed tests. It enables the complete test to run at much higher frequencies equal or close to the one in functional mode. It will be shown, that a lesser number of test cycles can be achieved compared to other published solutions. The test cycle per net based on a simple test pattern generator algorithm without test pattern compression is below 1 for larger designs and is independent of the design size. The structure allows an additional on-chip debugging signal visibility for each register. The method is backward compatible to full scan designs and existing test pattern generators and simulators can be used with a minor enhancement. It is shown how to combine the proposed solution with built-in self-test  (BIST)  and  massive parallel   scan   chains.   The   results   are   observed   on   Xilinx XC3s1600e-5fgg48

Demonstration of monolithically integrated graphene interconnects for low-power CMOS applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 129-141).In recent years, interconnects have become an increasingly difficult design challenge as their relative performance has not improved at the same pace with transistor scaling. The specifications for complex features, clock frequency, supply current, and number of I/O resources have added even greater demands for interconnect performance. Furthermore, the resistivity of copper begins to degrade at smaller line widths due to increased scattering effects. Graphene has gathered much interest as an interconnect material due to its high mobility, high current carrying capacity, and high thermal conductivity. DC characterization of sub-50 nm graphene interconnects has been reported but very few studies exist on evaluating their performance when integrated with CMOS. Integrating graphene with CMOS is a critical step in establishing a path for graphene electronics. In this thesis, we characterize the performance of integrated graphene interconnects and demonstrate two prototype CMOS chips. A 0.35 prm CMOS chip implements an array of transmitter/receivers to analyze end-to-end data communication on graphene wires. Graphene sheets are synthesized by chemical vapor deposition, which are then subsequently transferred and patterned into narrow wires up to 1 mm in length. A low-swing signaling technique is applied, which results in a transmitter energy of 0.3-0.7 pJ/bit/mm, and a total energy of 2.4-5.2 pJ/bit/mm. We demonstrate a minimum voltage swing of 100 mV and bit error rates below 2x10-10. Despite the high sheet resistivity of graphene, integrated graphene links run at speeds up to 50 Mbps. Finally, a subthreshold FPGA was implemented in 0.18 pm CMOS. We demonstrate reliable signal routing on 4-layer graphene wires which replaces parts of the interconnect fabric. The FPGA test chip includes a 5x5 logic array and a TDC-based tester to monitor the delay of graphene wires. The graphene wires have 2.8x lower capacitance than the reference metal wires, resulting in up to 2.11x faster speeds and 1.54x lower interconnect energy when driven by a low-swing voltage of 0.4 V. This work presents the first graphene-based system application and demonstrates the potential of using low capacitance graphene wires for ultra-low power electronics.by Kyeong-Jae Lee.Ph.D

FPGA ARCHITECTURE AND VERIFICATION OF BUILT IN SELF-TEST (BIST) FOR 32-BIT ADDER/SUBTRACTER USING DE0-NANO FPGA AND ANALOG DISCOVERY 2 HARDWARE

The integrated circuit (IC) is an integral part of everyday modern technology, and its application is very attractive to hardware and software design engineers because of its versatility, integration, power consumption, cost, and board area reduction. IC is available in various types such as Field Programming Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), System on Chip (SoC) architecture, Digital Signal Processing (DSP), microcontrollers (μC), and many more. With technology demand focused on faster, low power consumption, efficient IC application, design engineers are facing tremendous challenges in developing and testing integrated circuits that guaranty functionality, high fault coverage, and reliability as the transistor technology is shrinking to the point where manufacturing defects of ICs are affecting yield which associates with the increased cost of the part. The competitive IC market is pressuring manufactures of ICs to develop and market IC in a relatively quick turnaround which in return requires design and verification engineers to develop an integrated self-test structure that would ensure fault-free and the quality product is delivered on the market. 70-80% of IC design is spent on verification and testing to ensure high quality and reliability for the enduser. To test complex and sophisticated IC designs, the verification engineers must produce laborious and costly test fixtures which affect the cost of the part on the competitive market. To avoid increasing the part cost due to yield and test time to the end-user and to keep up with the competitive market many IC design engineers are deviating from complex external test fixture approach and are focusing on integrating Built-in Self-Test (BIST) or Design for Test (DFT) techniques onto IC’s which would reduce time to market but still guarantee high coverage for the product. Understanding the BIST, the architecture, as well as the application of IC, must be understood before developing IC. The architecture of FPGA is elaborated in this paper followed by several BIST techniques and applications of those BIST relative to FPGA, SoC, analog to digital (ADC), or digital to analog converters (DAC) that are integrated on IC. Paper is concluded with verification of BIST for the 32-bit adder/subtracter designed in Quartus II software using the Analog Discovery 2 module as stimulus and DE0-NANO FPGA board for verification

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

An Ultra-Low-Energy, Variation-Tolerant FPGA Architecture Using Component-Specific Mapping

As feature sizes scale toward atomic limits, parameter variation continues to increase, leading to increased margins in both delay and energy. Parameter variation both slows down devices and causes devices to fail. For applications that require high performance, the possibility of very slow devices on critical paths forces designers to reduce clock speed in order to meet timing. For an important and emerging class of applications that target energy-minimal operation at the cost of delay, the impact of variation-induced defects at very low voltages mandates the sizing up of transistors and operation at higher voltages to maintain functionality. With post-fabrication configurability, FPGAs have the opportunity to self-measure the impact of variation, determining the speed and functionality of each individual resource. Given that information, a delay-aware router can use slow devices on non-critical paths, fast devices on critical paths, and avoid known defects. By mapping each component individually and customizing designs to a component's unique physical characteristics, we demonstrate that we can eliminate delay margins and reduce energy margins caused by variation. To quantify the potential benefit we might gain from component-specific mapping, we first measure the margins associated with parameter variation, and then focus primarily on the energy benefits of FPGA delay-aware routing over a wide range of predictive technologies (45 nm--12 nm) for the Toronto20 benchmark set. We show that relative to delay-oblivious routing, delay-aware routing without any significant optimizations can reduce minimum energy/operation by 1.72x at 22 nm. We demonstrate how to construct an FPGA architecture specifically tailored to further increase the minimum energy savings of component-specific mapping by using the following techniques: power gating, gate sizing, interconnect sparing, and LUT remapping. With all optimizations considered we show a minimum energy/operation savings of 2.66x at 22 nm, or 1.68--2.95x when considered across 45--12 nm. As there are many challenges to measuring resource delays and mapping per chip, we discuss methods that may make component-specific mapping more practical. We demonstrate that a simpler, defect-aware routing achieves 70% of the energy savings of delay-aware routing. Finally, we show that without variation tolerance, scaling from 16 nm to 12 nm results in a net increase in minimum energy/operation; component-specific mapping, however, can extend minimum energy/operation scaling to 12 nm and possibly beyond.</p

High-speed Analog-to-digital Converters For Modern Satellite Receivers: Design Verification Test And Sensitivity Analysis

Mixed-signal System-on-chip devices such as analog-to-digital converters (ADCs) have become increasingly prevalent in the semiconductor industry. Since the complexity and applications are different for each device, complex testing and characterization methods are required. Specifically, signal integrity in I/O interfaces requires that standard RF design and test techniques must be integrated into mixed signal processes. While such techniques may be difficult to implement, on-chip test-vehicles and RF circuitry offer the possibility of wireless approaches to chip testing. This would eliminate expensive wafer probing solution to verify the design of high-speed ADC functionality currently required for high-speed product evaluation. This thesis describes a new high-speed analog-to-digital converter test methodology. The target systems used on-chip digital de-multiplexing and clock distribution. A detail sequence of performance testing operations is presented. Digital outputs are post processed and fed into a computer-aided ADC performance characterization tool which is custom-developed in a MATLAB GUI. The problems of high sampling rate ADC testing are described. The test methodologies described reduce test costs and overcome many test hardware limitations. As our focus is on satellite receiver systems, we emphasize the measurement of inter-modulation distortion and effective resolution bandwidth. As a primary characterization component, Fourier analysis is used and we address the issue of sample window adjustment to eliminate spectral leakage and false spur generation. A 6-bit 800 MSamples/sec dual channel SiGe-based ADC is used as a target example and investigated on the corner lot process variations to determine the impact of process variations and the sensitivity of the ADCs to critical process parameter variations