6,675 research outputs found
Architectural Design and Implementation of Bit Error Rate Tester on FPGA
FPGAs have witnessed an increased use of dedicated communication interfaces. With their increased use, it is becoming critical to test and properly characterize all such interfaces. Bit error rate (BER) characteristic is one of the basic measures of the performance of any digital communication system. This thesis presents a scheme for BER testing in FPGAs, with a few orders of magnitude speedup compared to other tradition methods. Where the using of hardware emulation by FPGA is very interested for most researches and designers in present time, because it has properties such as flexibility in reprogramming it and prepare it according to the user need, so we chose this technique in this thesis as an implementation environment to the proposed scheme. The proposed scheme mainly consists of an essential scheme core: a bit error rate tester (BERT), by using MATLAB Simulink software in the beginning, then composition this software on FPGA chip (spartan-6 type) by using ISE 14.2 software. The results shows very good agreement between software representation and the implementation on FPGA chip
An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links
Nowadays spike-based brain processing emulation is
taking off. Several EU and others worldwide projects are
demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or
NeuroGrid. The larger the brain process emulation on silicon is,
the higher the communication performance of the hosting
platforms has to be. Many times the bottleneck of these system
implementations is not on the performance inside a chip or a
board, but in the communication between boards. This paper
describes a novel modular Address-Event-Representation (AER)
FPGA-based (Spartan6) infrastructure PCB (the AER-Node
board) with 2.5Gbps LVDS high speed serial links over SATA
cables that offers a peak performance of 32-bit 62.5Meps (Mega
events per second) on board-to-board communications. The
board allows back compatibility with parallel AER devices
supporting up to x2 28-bit parallel data with asynchronous
handshake. These boards also allow modular expansion
functionality through several daughter boards. The paper is
focused on describing in detail the LVDS serial interface and
presenting its performance.Ministerio de Ciencia e Innovación TEC2009-10639-C04-02/01Ministerio de Economía y Competitividad TEC2012-37868-C04-02/01Junta de Andalucía TIC-6091Ministerio de Economía y Competitividad PRI-PIMCHI-2011-076
From FPGA to ASIC: A RISC-V processor experience
This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC
A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization
A new generation of radio telescopes is achieving unprecedented levels of
sensitivity and resolution, as well as increased agility and field-of-view, by
employing high-performance digital signal processing hardware to phase and
correlate large numbers of antennas. The computational demands of these imaging
systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the
number of independent beams, and N is the number of antennas. The
specifications of many new arrays lead to demands in excess of tens of PetaOps
per second.
To meet this challenge, we have developed a general purpose correlator
architecture using standard 10-Gbit Ethernet switches to pass data between
flexible hardware modules containing Field Programmable Gate Array (FPGA)
chips. These chips are programmed using open-source signal processing libraries
we have developed to be flexible, scalable, and chip-independent. This work
reduces the time and cost of implementing a wide range of signal processing
systems, with correlators foremost among them,and facilitates upgrading to new
generations of processing technology. We present several correlator
deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes
parameter application deployed on the Precision Array for Probing the Epoch of
Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31
pages. v2: corrected typo, v3: corrected Fig. 1
Design and construction of a Cherenkov imager for charge measurement of nuclear cosmic rays
A proximity focusing Cherenkov imager called CHERCAM, has been built for the
charge measurement of nuclear cosmic rays with the CREAM instrument. It
consists of a silica aerogel radiator plane across from a detector plane
equipped with 1,600 1" diameter photomultipliers. The two planes are separated
by a ring expansion gap. The Cherenkov light yield is proportional to the
charge squared of the incident particle. The expected relative light collection
accuracy is in the few percents range. It leads to an expected single element
separation over the range of nuclear charge Z of main interest 1 < Z < 26.
CHERCAM is designed to fly with the CREAM balloon experiment. The design of the
instrument and the implemented technical solutions allowing its safe operation
in high altitude conditions (radiations, low pressure, cold) are presented.Comment: 24 pages, 19 figure
An FPGA-based real-time event sampler
This paper presents the design and FPGA-implementation of a sampler that is suited for sampling real-time events in embedded systems. Such sampling is useful, for example, to test whether real-time events are handled in time on such systems. By designing and implementing the sampler as a logic analyzer on an FPGA, several design parameters can be explored and easily modified to match the behavior of different kinds of embedded systems. Moreover, the trade-off between price and performance becomes easy, as it mainly exists of choosing the appropriate type and speed grade of an FPGA family
The Topological Processor for the future ATLAS Level-1 Trigger: from design to commissioning
The ATLAS detector at LHC will require a Trigger system to efficiently select
events down to a manageable event storage rate of about 400 Hz. By 2015 the LHC
instantaneous luminosity will be increased up to 3 x 10^34 cm-2s-1, this
represents an unprecedented challenge faced by the ATLAS Trigger system. To
cope with the higher event rate and efficiently select relevant events from a
physics point of view, a new element will be included in the Level-1 Trigger
scheme after 2015: the Topological Processor (L1Topo). The L1Topo system,
currently developed at CERN, will consist initially of an ATCA crate and two
L1Topo modules. A high density opto-electroconverter (AVAGO miniPOD) drives up
to 1.6 Tb/s of data from the calorimeter and muon detectors into two high-end
FPGA (Virtex7-690), to be processed in about 200 ns. The design has been
optimized to guarantee excellent signal in- tegrity of the high-speed links and
low latency data transmission on the Real Time Data Path (RTDP). The L1Topo
receives data in a standalone protocol from the calorimeters and muon detectors
to be processed into several VHDL topological algorithms. Those algorithms
perform geometrical cuts, correlations and calculate complex observables such
as the invariant mass. The output of such topological cuts is sent to the
Central Trigger Processor. This talk focuses on the relevant high-density
design characteristic of L1Topo, which allows several hundreds optical links to
processed (up to 13 Gb/s each) using ordinary PCB material. Relevant test
results performed on the L1Topo prototypes to characterize the high-speed links
latency (eye diagram, bit error rate, margin analysis) and the logic resource
utilization of the algorithms are discussed.Comment: 5 pages, 6 figure
Field test of quantum key distribution in the Tokyo QKD Network
A novel secure communication network with quantum key distribution in a
metropolitan area is reported. Different QKD schemes are integrated to
demonstrate secure TV conferencing over a distance of 45km, stable long-term
operation, and application to secure mobile phones.Comment: 21 pages, 19 figure
The STAR MAPS-based PiXeL detector
The PiXeL detector (PXL) for the Heavy Flavor Tracker (HFT) of the STAR
experiment at RHIC is the first application of the state-of-the-art thin
Monolithic Active Pixel Sensors (MAPS) technology in a collider environment.
Custom built pixel sensors, their readout electronics and the detector
mechanical structure are described in detail. Selected detector design aspects
and production steps are presented. The detector operations during the three
years of data taking (2014-2016) and the overall performance exceeding the
design specifications are discussed in the conclusive sections of this paper
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