Reliability in Power Electronics and Power Systems

L'abstract è presente nell'allegato / the abstract is in the attachmen

Test Solution for Heatsinks in Power Electronics Applications

Power electronics technology is widely used in several areas, such as in the railways, automotive, electric vehicles, and renewable energy sectors. Some of these applications are safety critical, e.g., in the automotive domain. The heat produced by power devices must be eciently dissipated to allow them to work within their operational thermal limits. Moreover, numerous ageing eects are due to thermal stress, which causes mechanical issues. Therefore, the reliability of a circuit depends on its dissipation system, even if it consists of a simple passive heatsink mounted on the power device. During the Printed Circuit Board (PCB) production, an incorrect assembly of the heatsink can cause a worse heat dissipation with a significant increase of the junction temperatures (Tj). In this paper, three possible test strategies are compared for testing the correct assembling of heatsinks. The considered strategies are used at the PCB end-manufacturing. The eectiveness of the dierent test methods considered is assessed on a case study corresponding to a Power Supply Unit (PSU)

Optimal Tuning of AGDs Parameters and a Technique for Testing the Correct Mounting of Heatsinks on Power Transistors

L'abstract è presente nell'allegato / the abstract is in the attachmen

Characterization Methodology, Modeling, and Converter Design for 600 V Enhancement-Mode GaN FETs

Gallium Nitride (GaN) power devices are an emerging technology that have only become available commercially in the past few years. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This dissertation reviews the unique characteristics, commercial status, and design challenges that surround GaN FETs, in order to provide sufficient background to potential GaN-based converter designers.Methodology for experimentally characterizing a GaN FET was also presented, including static characterization with a curve tracer and impedance analyzer, as well as dynamic characterization in a double pulse test setup. This methodology was supplemented by additional tests to determine losses caused by Miller-induced cross talk, and the tradeoff between these losses and overlap losses was studied for one example device.Based on analysis of characterization results, a simplified model was developed to describe the overall switching behavior and some unique features of the device. The impact of the Miller effect during the turn-on transient was studied, as well as the dynamic performance of GaN at elevated temperature.Furthermore, solutions were proposed for several key design challenges in GaN-based converters. First, a driver-integrated overcurrent and short-circuit protection scheme was developed, based on the relationship between gate voltage and drain current in GaN gate injection transistors. Second, the limitations on maximum utilization of current and voltage in a GaN FET were studied, particularly the voltage overshoots following turn-on and turn-off switching transients, and the effective cooling of GaN FETs in higher power operation. A thermal design was developed for heat extraction from bottom-cooled surface-mount devices. These solutions were verified in a GaN-based full-bridge single-phase inverter

UPS-laitteen vian erotuskyvyn parantaminen

UPS devices are utilized to ensure a constant and undisturbed power supply for critical loads. If a fault occurs in the AC grid that normally supplies the load, the UPS device will instantly begin to supply power from its batteries via the inverter to the load. However, if a fault, such as a short circuit, occurs in the load side of the UPS when the UPS is supplying power from its batteries, the UPS must be able to supply enough fault current to clear the circuit breaker closest to the fault location and isolate the fault before the UPS itself trips to overcurrent. The maximum output current of the UPS is intentionally limited in time and magnitude to prevent power semiconductor components of the UPS inverter from suffering overcurrent damages. The problem is that UPS devices must be often oversized in terms of rated power so that a sufficient fault clearing capability of the UPS to clear respective circuit breakers in the load side is achieved. Thus, the spare power which results from oversizing the UPS is dispensable during normal operation of the UPS. This thesis aims to find economical ways to improve the fault clearing capability of a UPS device. Hence, a simulation model is developed which can be used to estimate how much the fault clearing capability of a UPS device may be improved by installing IGBTs and diodes in parallel to the main circuit of the UPS inverter. Current limit values of the UPS inverter and number of parallel connected IGBTs and diodes in the main circuit of the inverter are adjustable in the simulation model. Power losses and junction temperatures of IGBTs and diodes are calculated based on input data which may be obtained from datasheets of IGBTs and diodes. The solution to improve the fault clearing capability of a UPS device by adding IGBTs and diodes in parallel to the main circuit of the inverter is compared from economical and technical point of view to the use of an external fault clearing circuitry which is another worthy solution to improve the fault clearing capability of a UPS device. Cost comparison conducted between the two solutions revealed that improving the fault clearing capability of a 20 kW UPS device by adding IGBTs and diodes in parallel to the main circuit of the inverter may result in 20–30% higher costs than using the fault clearing circuitry. Furthermore, the fault clearing circuitry may be technically a more feasible solution to be applied for existing UPS devices than the change in IGBT and diode configuration.UPS-laitteita käytetään varmistamaan jatkuva ja häiriötön sähkönsyöttö kriittisille kuormille. UPS-laite alkaa välittömästi syöttää sähköä akustostaan vaihtosuuntaajan kautta kuormalle, jos kuormaa normaalisti syöttävässä vaihtosähköverkossa syntyy vika. Jos UPS laitteen kuormapuolella syntyy kuitenkin vika, kuten oikosulku, kun UPS laite syöttää sähköä kuormalle akustostaan, UPS-laitteen täytyy pystyä syöttämään tarpeeksi vikavirtaa, jotta lähinnä vikapaikkaa oleva katkaisija avautuu ja erottaa vian ennen kuin UPS-laite katkaisee sähkönsyötön ylivirran vuoksi. UPS-laitteen maksimilähtövirta on tarkoituksellisesti rajoitettu ajalliselta kestoltaan ja suuruudeltaan, mikä ehkäisee UPS-laitteen vaihtosuuntaajassa olevien tehopuolijohdekomponenttien vaurioitumista ylivirran vuoksi. Ongelmana on, että UPS-laitteita joudutaan ylimitoittamaan nimellisteholtaan, jotta niille saadaan riittävän korkea vian erotuskyky laukaisemaan kuormapuolen katkaisijat vikatilanteessa. Tällöin UPS-laitteen ylimitoittamisesta syntyvä lisäteho on kuitenkin tarpeetonta UPS-laitteen normaalin toiminnan aikana. Tämän työn tarkoituksena on löytää taloudellisia keinoja parantaa UPS-laitteen vian erotuskykyä. Työssä kehitettiin simulointimalli, jolla voidaan arvioida, kuinka paljon UPS-laitteen vian erotuskykyä voidaan parantaa kytkemällä IGBT- ja diodikomponentteja rinnan UPS-laitteen vaihtosuuntaajan pääpiiriin. Vaihtosuuntaajan virtarajoja ja rinnankytkettävien IGBT- ja diodikomponenttien määrää voidaan säädellä simulaatiomallissa. IGBT- ja diodikomponenttien tehohäviöiden ja liitoslämpötilojen laskenta perustuu niiden datalehdistä saataviin tietoihin, jotka syötetään simulaatiomallille. Ratkaisua, jossa UPS-laitteen vian erotuskykyä parannetaan kytkemällä IGBT- ja diodikomponentteja rinnan vaihtosuuntaajan pääpiiriin, verrataan taloudellisesta ja teknisestä näkökulmasta ulkoiseen vian erotuspiiriin, joka on toinen varteenotettava ratkaisu, jolla UPS-laitteen vian erotuskykyä voidaan parantaa. Ratkaisuille tehtiin kustannusvertailu, josta selvisi, että parantamalla nimellisteholtaan 20 kW:n UPS-laitteen vian erotuskykyä lisäämällä IGBT- ja diodikomponentteja rinnan vaihtosuuntaajan pääpiiriin lisää se kustannuksia 20–30% verrattuna ulkoisen vian erotuspiirin käyttöön. Vian erotuspiirin kytkeminen on lisäksi teknisesti helpompi toteuttaa jo olemassa oleviin UPS-laitteisiin verrattuna siihen, että niihin tehtäisiin vaadittavat IGBT- ja diodikomponenttien laitekokoonpanomuutokset

Multilevel Converters for Battery Energy Storage: How Many Levels and Why?

This work explores the potential benefits of cascaded H-bridge multilevel converters in low-voltage applications, particularly grid-attached battery energy storage systems (BESS). While some benefits of these are discussed in literature, this work seeks to create practical, quantitative models for system performance in terms of a number of key performance parameters. These models are then used to find the trends in these performance parameters with an increasingly high order converter, starting to answer the question of how many levels are best. The system performance parameters modelled are power loss, thermal performance and reliability. Wherever practical models and assumptions are validated, be that experimentally or through comparison with existing methods – this work includes a number of experimental series. The resulting trends explored highlight a number of interesting trends, principally: total power loss can be much lower, particularly at high switching frequencies; system thermal performance can be much improved owing to more efficient heatsink utilisation; and due to these thermal benefits, the system reliability based on switching device failure does not suffer as one might expect, and can in fact be higher under some conditions. The investigation also considers the use of cutting-edge switching device technology, such as gallium nitride power transistors, which a multilevel converter enables the use of, and in turn can significantly reduce power dissipation and increase switching frequency. Overall, the work adds new arguments in favour of multilevel converters in such applications and lowers the barrier to practical implementation by answering a number of questions a designer would likely ask. The key novel contributions of this work are the results of the trends that were found in terms of converter power loss, system thermal performance and switching device reliability with respect to multilevel converter order – with the methodologies created for these being somewhat novel in their own right. Along the way, however, other novel work was conducted including: an experimental investigation in to the accuracy of voltage-capacitance curves provided by manufacturers; experimental derivation of relationships for predicting MOSFET body diode performance from readily available device parameters; analysis showing the potential impact of GaN devices on converter efficiency; an experimental validation of GaN device gate turn-on energy; creation and validation of empirical relationship for predicting how heatsink performance varies with more devices of a smaller size; as well as an exploration of whether the extreme small size of some modern power transistors could lead to unexpected thermal cycling issues

Enhancement of fault current contribution from inverter-based resources

The reduction in levels of fault current infeed as inverter-based resources (IBR) displace synchronous machines undermines the ability of a conventional protection system to identify and isolate faults in an effective manner and is therefore a concern for system operators (SOs). This observation provided the motivation to investigate the limitations of IBRs when injecting fault current and to explore how these limitations might be overcome. This thesis investigates techniques aimed at significantly increasing Fault Current Contribution (FCC) from an IBR system so that renewable energy resources can continue to be deployed without compromising the protection system. The techniques for enhancing FCC are at three different levels of an IBR system: at semiconductor or device level, circuit level and system level. The first study uses phase change materials (PCM) to provide a short-term overload rating to insulated-gate bipolar transistors (IGBTs) and found them to have very limited potential to provide FCC. A Finite Element Analysis (FEA) of heat-flow concluded that, although the PCM was useful for dealing with short over-load currents, it was unsuitable for facilitating large fault currents of several times normal load current. The view was that if the fault current cannot be created at device level through better thermal management, then a circuit level innovation would be required. The second study investigates series/parallel switching of submodules in modular converters. This takes advantage of the fact that during a fault, the line voltage is reduced, and if it falls below 0.5 pu then half of the sub-modules (SMs) can be put into parallel with the other half to double the FCC (2 pu) at half the voltage (0.5 pu). Similarly, if the voltage drops below 0.25 pu, parallel connection of four groups of SMs would enable 4 pu current capability. A model of a static synchronous compensator (STATCOM) was developed, inspired by the alternate arm converter (AAC), with the director switch of the AAC used as part of the reconfiguration circuit. The conclusion of this study was that the penalty paid in power losses in the additional semiconductor devices used for reconfiguration is reasonable for the 2 pu FCC case but not at the 4 pu FCC case. The third study was based on circuit reconfiguration but beyond the converter itself and in this case the windings of the coupling transformer of a STATCOM. Sections of winding were switched using thyristors to tap-change the transformer by a large factor. Using the proposed thyristor-based electronic tap-changer (eTC), the number of turns of the grid-side winding was reduced during a voltage dip, so that larger current can be delivered to the network for the same converter current. The STATCOM was controlled in the natural frame (abc frame) and this control is used to actively drive the currents in the tap-changer thyristors to zero when needed so that they can be commuted rapidly. The transformer was configured to give a normal ratio of 1:4 and be able to tap-down to 1:2 and 1:1 to increase FCC to 2 pu or 4 pu. Theoretical analysis of, and operating principles for, the proposed eTC, together with their associated control schemes, are verified by time-domain simulation at full-scale. The case-study circuit demonstrates delivery of substantial fault current contribution (FCC) of up to 4 pu at the point of common coupling (PCC) in less than half a cycle (10 ms) after detection of three- and single-phase faults. The results demonstrate that the proposed eTC is a good candidate for the enhancement of fault current from IBR systems that employ coupling transformers, allowing them thereby to make a contribution to future electricity networks dominated by IBR.Open Acces

Assessing the effectiveness of different test approaches for power devices in a PCB

Power electronic systems employing Printed Circuit Boards (PCBs) are broadly used in many applications, including some safety-critical ones. Several standards (e.g., ISO26262 for the automotive sector and DO-178 for avionics) mandate the adoption of effective test procedures for all electronic systems. However, the metrics to be used to compute the effectiveness of the adopted test procedures are not so clearly defined for power devices and systems. In the last years, some commercial fault simulation tools (e.g., DefectSim by Mentor Graphics and TestMAX by Synopsys) for analog circuits have been introduced, together with some new fault models. With these new tools, systematic analog fault simulation finally became practically feasible. The aim of this paper is twofold: first, we propose a method to extend the usage of the new analog fault models to power devices, thus allowing to compute a Fault Coverage figure for a given test. Secondly, we adopt the method on a case study, for which we quantitatively evaluate the effectiveness of some test procedures commonly used at the PCB level for the detection of faults inside power devices. A typical Power Supply Unit (PSU) used in industrial products, including power transistors and power diodes, is considered. The analysis of the gathered results shows that using the new method we can identify the main points of strength / weakness of the different test solutions in a quantitative and deterministic manner, and pinpoint the faults escaping to each one

Design of a 350 kW Silicon Carbide Based 3-phase Inverter with Ultra-Low Parasitic Inductance

The objective of this thesis is to present a design for a low parasitic inductance, high power density 3-phase inverter using silicon-carbide power modules for traction application in the electric vehicles with a power rating of 350 kW. With the market share of electric vehicles continuing to grow, there is a great opportunity for wide bandgap semiconductors such as silicon carbide (SiC) to improve the efficiency and size of the motor drives in these applications. In order to accomplish this goal, careful design and selection of each component in the system for optimum performance from an electrical, mechanical, and thermal standpoint. At each level from top to bottom the inverter sub-assembly performance will be characterized including DC link inductance, power module switching losses, and inverter efficiency. The core power electronics will be built around the latest generation of 1200 V half-bridge SiC power modules with an ultra-low inductance dc bus capacitor and laminated bussing, fast switching speed and very low loss. A custom controller and gate drivers are designed capable of driving the power electronics at high switching speed without disturbance from high dv/dt noise. Finally, the inverter is packaged into a complete system and tested under various conditions with a 3-phase inductive load simulating a motor load. The test results presented include output power and efficiency at various bus voltages, currents, and switching frequencies