648 research outputs found
The integration of on-line monitoring and reconfiguration functions using IEEE1149.4 into a safety critical automotive electronic control unit.
This paper presents an innovative application of IEEE 1149.4 and the integrated diagnostic reconfiguration (IDR) as tools for the implementation of an embedded test solution for an automotive electronic control unit, implemented as a fully integrated mixed signal system. The paper describes how the test architecture can be used for fault avoidance with results from a hardware prototype presented. The paper concludes that fault avoidance can be integrated into mixed signal electronic systems to handle key failure modes
Using Relocatable Bitstreams for Fault Tolerance
This research develops a method for relocating reconfigurable modules on the Virtex-II (Pro) family of Field Programmable Gate Arrays (FPGAs). A bitstream translation program is developed which correctly changes the location of a partial bitstream that implements a module on the FPGA. To take advantage of relocatable modules, three fault-tolerance circuit designs are developed and tested. This circuit can operate through a fault by efficiently removing the faulty module and replacing it with a relocated module without faults. The FPGA can recover from faults at a known location, without the need for external intervention using an embedded fault recovery system. The recovery system uses an internal PowerPC to relocate the modules and reprogram the FPGA. Due to the limited architecture of the target FPGA and Xilinx tool errors, an FPGA with automatic fault recovery could not be demonstrated. However, the various components needed to do this type of recovery have been implemented and demonstrated individually
Analysis and Evaluation of PUF-based SoC Designs for Security Applications
This paper presents a critical analysis and statistical evaluation of two categories of Physically Unclonable Functions (PUFs): ring oscillator PUF and a new proposed adapted latch based PUF. The main contribution is that of measuring the properties of PUF which provide the basic information for using them in security applications. The original method involved the conceptual design of adapted latch based PUFs and ring oscillator PUFs in combination with peripheral devices in order to create an environment for experimental analysis of PUF properties. Implementation, testing and analysis of results followed. This approach has applications on high level security
Design-for-delay-testability techniques for high-speed digital circuits
The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud
getting more and more important
A Survey of Fault-Injection Methodologies for Soft Error Rate Modeling in Systems-on-Chips
The development of process technology has increased system performance, but the system failure probability has also significantly increased. It is important to consider the system reliability in addition to the cost, performance, and power consumption. In this paper, we describe the types of faults that occur in a system and where these faults originate. Then, fault-injection techniques, which are used to characterize the fault rate of a system-on-chip (SoC), are investigated to provide a guideline to SoC designers for the realization of resilient SoCs
Interconnect yield analysis and fault tolerance for field programmable gate arrays
Imperial Users onl
Building Blocks for Adaptive Modular Sensing Systems
This thesis contributes towards the development of systems and strategies by which sensor and actuator components can be combined to produce flexible and robust sensor systems for a given application. A set of intelligent modular blocks (building blocks) have been created from which composite sensors (made up of multiple sensor and actuator components) can be rapidly reconfigured for the construction of Adaptive Modular Sensing Systems. The composite systems are expected to prove useful in several application domains including industrial control, inspection systems, mobile robotics, monitoring and data acquisition. The intelligent building blocks, referred to as transducer interface modules, contain embedded knowledge about their capabilities and how they can interact with other modules. These modules encapsulate a general purpose modular hardware architecture that provides an interface between the sensors, the actuators, and the communication medium. The geometry of each transducer interface module is a cube. A connector mechanism implemented on each face of the module enables physical connection of the modules. Each module provides a core functionality and can be connected to other modules to form more capable composite sensors. Once the modules are combined, the capabilities (e.g., range, resolution, sample rate, etc.) and functionality (e.g., temperature measurement) of the composite sensor is determined and communicated to other sensors in the enviornment. For maximum flexibility, a distributed software architecture is executed on the blocks to enable automatic acquisition of configuration-specific algorithms. This logical algorithm imparts a collective identity to the composite group, and processes data based on the capabilities and functionalities of the transducers present in the system. A knowledge representation scheme allows each module in the composite group to store and communicate its functionality and capabilities to other connected modules in the system
LASER Tech Briefs, Spring 1994
Topics in this Laser Tech Brief include: Electronic Components and Circuits. Electronic Systems, Physical Sciences, Materials, Mechanics, Fabrication Technology, and books and reports
A Remote Verification Framework to Assess the Robustness of Circuits to Soft Faults
The growing number of circuits implemented in Field
Programmable Gate Arrays (FPGAs) and the increased
susceptibility, due to higher integration levels, of these devices to
soft faults caused by radiation at ground level is leading the
scientific and technical community to the study of new fault
tolerant designs and solutions, and how they can be verified and
validated. Using fault injection techniques and enhanced debug
tools to inject faults in a circuit and observing its behaviour in the
presence of such faults, respectively, is a proven solution for the
previous verification and validation problem. This paper presents
the underlying concepts for a remote verification framework to
assess the robustness of circuits to soft faults. It comprises a
verification platform and a set of verification services that can be
used in a remote or local fashions.info:eu-repo/semantics/publishedVersio
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