1,553 research outputs found
Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models
Speech recognition is a computationally demanding task, particularly the stage which uses Viterbi decoding for converting pre-processed speech data into words or sub-word units. Any device that can reduce the load on, for example, a PCâs processor, is advantageous. Hence we present FPGA implementations of the decoder based alternately on discrete and continuous hidden Markov models (HMMs) representing monophones, and demonstrate that the discrete version can process speech nearly 5,000 times real time, using just 12% of the slices of a Xilinx Virtex XCV1000, but with a lower recognition rate than the continuous implementation, which is 75 times faster than real time, and occupies 45% of the same device
The ARIEL Instrument Control Unit design for the M4 Mission Selection Review of the ESA's Cosmic Vision Program
The Atmospheric Remote-sensing Infrared Exoplanet Large-survey mission
(ARIEL) is one of the three present candidates for the ESA M4 (the fourth
medium mission) launch opportunity. The proposed Payload will perform a large
unbiased spectroscopic survey from space concerning the nature of exoplanets
atmospheres and their interiors to determine the key factors affecting the
formation and evolution of planetary systems. ARIEL will observe a large number
(>500) of warm and hot transiting gas giants, Neptunes and super-Earths around
a wide range of host star types, targeting planets hotter than 600 K to take
advantage of their well-mixed atmospheres. It will exploit primary and
secondary transits spectroscopy in the 1.2-8 um spectral range and broad-band
photometry in the optical and Near IR (NIR). The main instrument of the ARIEL
Payload is the IR Spectrometer (AIRS) providing low-resolution spectroscopy in
two IR channels: Channel 0 (CH0) for the 1.95-3.90 um band and Channel 1 (CH1)
for the 3.90-7.80 um range. It is located at the intermediate focal plane of
the telescope and common optical system and it hosts two IR sensors and two
cold front-end electronics (CFEE) for detectors readout, a well defined process
calibrated for the selected target brightness and driven by the Payload's
Instrument Control Unit (ICU).Comment: Experimental Astronomy, Special Issue on ARIEL, (2017
A Hierachical Infrastrucutre for SOC Test Management
HD2BIST - a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems - maximizes and simplifies the reuse of built-in test architectures. HD2BIST optimizes the flexibility for chip designers in planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system
Enabling Technologies for Silicon Microstrip Tracking Detectors at the HL-LHC
While the tracking detectors of the ATLAS and CMS experiments have shown
excellent performance in Run 1 of LHC data taking, and are expected to continue
to do so during LHC operation at design luminosity, both experiments will have
to exchange their tracking systems when the LHC is upgraded to the
high-luminosity LHC (HL-LHC) around the year 2024. The new tracking systems
need to operate in an environment in which both the hit densities and the
radiation damage will be about an order of magnitude higher than today. In
addition, the new trackers need to contribute to the first level trigger in
order to maintain a high data-taking efficiency for the interesting processes.
Novel detector technologies have to be developed to meet these very challenging
goals. The German groups active in the upgrades of the ATLAS and CMS tracking
systems have formed a collaborative "Project on Enabling Technologies for
Silicon Microstrip Tracking Detectors at the HL-LHC" (PETTL), which was
supported by the Helmholtz Alliance "Physics at the Terascale" during the years
2013 and 2014. The aim of the project was to share experience and to work
together on key areas of mutual interest during the R&D phase of these
upgrades. The project concentrated on five areas, namely exchange of
experience, radiation hardness of silicon sensors, low mass system design,
automated precision assembly procedures, and irradiations. This report
summarizes the main achievements
An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration
We empirically evaluate an undervolting technique, i.e., underscaling the
circuit supply voltage below the nominal level, to improve the power-efficiency
of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable
Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing
faults due to excessive circuit latency increase. We evaluate the
reliability-power trade-off for such accelerators. Specifically, we
experimentally study the reduced-voltage operation of multiple components of
real FPGAs, characterize the corresponding reliability behavior of CNN
accelerators, propose techniques to minimize the drawbacks of reduced-voltage
operation, and combine undervolting with architectural CNN optimization
techniques, i.e., quantization and pruning. We investigate the effect of
environmental temperature on the reliability-power trade-off of such
accelerators. We perform experiments on three identical samples of modern
Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification
CNN benchmarks. This approach allows us to study the effects of our
undervolting technique for both software and hardware variability. We achieve
more than 3X power-efficiency (GOPs/W) gain via undervolting. 2.6X of this gain
is the result of eliminating the voltage guardband region, i.e., the safe
voltage region below the nominal level that is set by FPGA vendor to ensure
correct functionality in worst-case environmental and circuit conditions. 43%
of the power-efficiency gain is due to further undervolting below the
guardband, which comes at the cost of accuracy loss in the CNN accelerator. We
evaluate an effective frequency underscaling technique that prevents this
accuracy loss, and find that it reduces the power-efficiency gain from 43% to
25%.Comment: To appear at the DSN 2020 conferenc
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