24 research outputs found

    Test exploration and validation using transaction level models

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    The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space. This paper presents test design space exploration and validation of test strategies and schedules using transaction level models (TLMs). Since many aspects of testing involve the transfer of a significant amount of test stimuli and responses, the communication-centric view of TLMs suits this purpose exceptionally wel

    Vector Operation Support for Transport Triggered Architectures

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    High performance and low power consumption requirements usually restrict the design process of embedded processors. Traditional design solutions do not apply to the requirements today, but instead demands exploiting varying levels of parallelism. In order to reduce design time and effort, a powerful toolset is required to design new parallel processors effectively. TTA-based Co-design Environment (TCE) is a toolset developed in Tampere University of Technology for designing customized parallel processors. It is based on a modular Transport Triggered Architecture (TTA) processor architecture template, which provides easy customization and allows exploiting instruction-level parallelism for high performance execution. Single Instruction, Multiple Data (SIMD) paradigm provides powerful data-level parallel vector computation for many applications in embedded processing. It is one of the most common ways to exploit parallelism in today's processor designs in order to gain greater execution efficiency and, therefore, to meet the performance requirements. This work describes how data-level parallel SIMD support is introduced and integrated to the TCE design flow for more diverse parallelism support. The support allows designers to customize and program processors with wide vector operations. The work presents the required modification points along with the new tools that were added to the toolset. Much weight is given for the retargetable compiler, which must be able to adapt to all resources on TTA machines. The added tools were required to provide as much automatic behavior as possible to maintain effective design flow. In addition, the thesis presents how the modifications and new features were verified

    Towards Establishing a Change Management Process at an Academic Research Laboratory Network

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    This report focuses on the evaluation and development of a change management process for the Regis University Academic Research Network (ARNe), and specifically the SEAD Practicum. The author originally proposed expanding on a security audit performed on the ARNe in 2008, and researched, evaluated and presents several risk assessment methodologies. This broad approach was later focused on the practical aspects of developing a change management process for the ARNe/SEAD Practicum, based on researching applicable standards and best practice guidance. A management questionnaire and user survey were developed and distributed to obtain valuable opinions and perspectives from the individuals most directly involved with the administration and use of the ARNe and SEAD Practicum portal

    Randomised testing of a microprocessor model using SMT-solver state generation

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    Low power digital signal processing

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