Multistage Switching Architectures for Software Routers

Software routers based on personal computer (PC) architectures are becoming an important alternative to proprietary and expensive network devices. However, software routers suffer from many limitations of the PC architecture, including, among others, limited bus and central processing unit (CPU) bandwidth, high memory access latency, limited scalability in terms of number of network interface cards, and lack of resilience mechanisms. Multistage PC-based architectures can be an interesting alternative since they permit us to i) increase the performance of single software routers, ii) scale router size, iii) distribute packet manipulation and control functionality, iv) recover from single-component failures, and v) incrementally upgrade router performance. We propose a specific multistage architecture, exploiting PC-based routers as switching elements, to build a high-speed, largesize,scalable, and reliable software router. A small-scale prototype of the multistage router is currently up and running in our labs, and performance evaluation is under wa

A Readout System for the STAR Time Projection Chamber

We describe the readout electronics for the STAR Time Projection Chamber. The system is made up of 136,608 channels of waveform digitizer, each sampling 512 time samples at 6-12 Mega-samples per second. The noise level is about 1000 electrons, and the dynamic range is 800:1, allowing for good energy loss ($dE/dx$) measurement for particles with energy losses up to 40 times minimum ionizing. The system is functioning well, with more than 99% of the channels working within specifications.Comment: 22 pages + 8 separate figures; 2 figures are .jpg photos to appear in Nuclear Instruments and Method

Custom automotive grade Linux image for production diagnostics

Dissertação de mestrado em Engenharia Eletrónica Industrial e Computadores (especialização em Sistemas Embebidos)Os sistemas presentes nos automóveis de hoje em dia, têm vindo a tornar-se cada vez mais complexos conforme as tecnologias e as preferências dos consumidores têm evoluído. Os sistemas, tais como consolas centrais ou paineis de instrumentos, têm o papel não só de informar os passageiros como também de entertenimento e ajuda na navegação. Estas e outras capacidades traduziram-se numa maior complexidade destes sistemas, tanto a nível do software como do hardware. A maior parte dos fornecedores de peças e equipamentos eletrónicos para a industria automóvel têm a necessidade de acelerar o processo de testes dos seus produtos, para poderem acompanhar a procura mantendo a qualidade. Para este fim, software de testes é usado nos sistemas desenvolvidos com o objetivo de testar o hardware e software desenvolvido para o cliente. No software de testes incluí-se o Production Diagnostic Software (PDS). A solução de PDS atualmente utilizada pela Bosch é composta por uma pilha de software, QNX a correr em paralelo com AUTOSAR da Vector. O AUTOSAR é um Real-Time Operative System (RTOS) usado como ponto de entrada dos comandos de diagnostico e oferece acesso ao hardware e à interface de comunicação. O QNX é um sistema UNIX de alto nível que lida com dispositivos externos, como ecrãs e audio. O Automotive Grade Linux (AGL), em comparação com outros sistemas operativos direcionados à indústria automóvel, é mais recente e apresenta software totalmente open-source. Devido a isto, apresenta custos reduzidos quando comparado com soluções closed-source e um maior grau de personalização em termos de código. Este projeto de dissertação implementou uma prova de conceito de um PDS usando o AGL como o unico sistema operativo, com o objetivo de competir e substituir, totalmente ou parcialmente, a pilha de software existente na solução atual da Bosch. A conclusão deste projeto de dissertação é que o AGL não consegue substituir a pilha de software devido à falta de qualidades real-time por parte do AGL. Mas, por outro lado, é um possível candidato a substituir o QNX na pilha de software, pois o AGL apresenta as mesmas capacidades que o QNX a menor custo e com maior personalização.The systems in today’s cars have become increasingly complex as technology and consumer prefer ences have evolved. Systems, such as center consoles or instrument clusters, have the role of not only inform passengers but also to entertain and aid navigation. These and other capabilities increased the complexity of these systems, in terms of software and hardware. Most suppliers of electronic parts and equipment to the automotive industry have the need to speed up the process of testing their products so that they can meet demand while maintaining quality. For this purpose, test software is used with the objective of testing the hardware and software developed for the client. Test software includes Production Diagnostic Software (PDS). The PDS solution currently used by Bosch is composed of a software stack, QNX running alongside Vectors AUTOSAR. AUTOSAR is a Real-Time Operative System (RTOS) used as the entry point for diagnostic commands and provides access to the hardware and communication interface. QNX is a high-level UNIX system that handles external devices, such as displays and audio. The Automotive Grade Linux (AGL), compared to other Operative Systems targeted at the automotive industry, is newer and features a open-source approach. Because of this, it offers lower costs when compared to other closed-source solutions and a higher level of customization of code. This dissertation project implemented a proof-of-concept of a PDS using AGL as the only operating system, with the aim to compete and replace, totally or partially, the existing software stack in the current Bosch solution. The conclusion drawn from this dissertation project is that AGL cannot replace the software stack, due to it’s lack of real-time capabilities. On the other hand, it is a possible candidate to replace QNX in the software stack, for the reason that AGL has the same capabilities at a lower cost and higher customization level

General purpose readout board {\pi} LUP: overview and results

This work gives an overview of the PCI-Express board $\pi$LUP, focusing on the motivation that led to its development, the technological choices adopted and its performance. The $\pi$LUP card was designed by INFN and University of Bologna as a readout interface candidate to be used after the Phase-II upgrade of the Pixel Detector of the ATLAS and CMS experiments at LHC. The same team in Bologna is also responsible for the design and commissioning of the ReadOut Driver (ROD) board - currently implemented in all the four layers of the ATLAS Pixel Detector (Insertable B-Layer, B-Layer, Layer-1 and Layer-2) - and acquired in the past years expertise on the ATLAS readout chain and the problematics arising in such experiments. Although the $\pi$LUP was designed to fulfill a specific task, it is highly versatile and might fit a wide variety of applications, some of which will be discussed in this work. Two 7$^{th}$-generation Xilinx FPGAs are mounted on the board: a Zynq-7 with an embedded dual core ARM Processor and a Kintex-7. The latter features sixteen 12.5$\,$Gbps transceivers, allowing the board to interface easily to any other electronic board, either electrically and/or optically, at the current bandwidth of the experiments for LHC. Many data-transmission protocols have been tested at different speeds, results will be discussed later in this work. Two batches of $\pi$LUP boards have been fabricated and tested, two boards in the first batch (version 1.0) and four boards in the second batch (version 1.1), encapsulating all the patches and improvements required by the first version.Comment: 6 pages, 10 figures, 21th Real Time Conference, winner of "2018 NPSS Student Paper Award Second Prize

Testing and Modeling Ethernet Switches and Networks for Use in ATLAS High-level Triggers

The ATLAS second level trigger will use a multi-layered LAN network to transfer 5 Gbyte/s detector data from ~1500 buffers to a few hundred processors. A model of the network has been constructed to evaluate its performance. A key component of the network model is a model of an individual switch, reproducing the behavior measured in real devices. A small number of measurable parameters are used to model a variety of commercial Ethernet switches. Using parameters measured on real devices, the impact on the overall network performance is modeled. In the Atlas context, both 100 Mbit and Gigabit Ethernet links are required. A system is described which is capable of characterizing the behavior of commercial switches with the required number of nodes under traffic conditions resembling those to be encountered in the Atlas experiment. Fast Ethernet traffic is provided by a high density, custom built tester based on FPGAs, programmed in Handel-C and VHDL, while the Gigabit Ethernet traffic is generated using Alteon NICs with custom firmware. The system is currently being deployed with 32 100Mbit ports and 16 Gigabit ports, and will be expanded to ~256 nodes of 100 Mbit and ~50 GBE nodes

F Prime: An Open-Source Framework for Small-Scale Flight Software Systems

Developing flight software for small-scale missions such as CubeSats and SmallSats is challenging. These missions typically have ambitious goals, modest budgets, and tight schedules. To meet these challenges, a good flight software framework is essential. Frameworks can provide an architecture, infrastructure, tools, and reusable software components, all of which can help developers deliver their code on time and on budget. In this paper we present F Prime, a free, open-source flight software framework developed at JPL and tailored to small-scale systems such as CubeSats, SmallSats, and instruments. F Prime comprises several elements: (1) an architecture that decomposes flight software into discrete components with well-defined interfaces; (2) a C++ framework that provides core capabilities such as message queues and threads; (3) tools for specifying components and connections and automatically generating code; (4) a growing collection of ready-to-use components; and (5) tools for testing flight software at the unit and integration levels. We describe the F Prime framework and tools and present our experience using them. We describe several enhancements to the framework currently underway in the areas of software design, software verification, and ground data systems for testing

Microsemi RTG4 Rev C Field Programmable Gate Array Single Event Effects (SEE) Heavy-Ion Test Report

The goal of this study was to perform an independent investigation of single event destructive and transient susceptibility of the Microsemi RTG4 device. The devices under test were the Microsemi RTG4 field programmable gate array (FPGA) Rev C. The devices under test will be referenced as the DUT or RTG4 Rev C throughout this document. The DUT was configured to have various test structures that are geared to measure specific potential susceptibilities of the device. DesignDevice susceptibility was determined by monitoring the DUT for Single Event Transient (SET) and Single Event Upset (SEU) induced faults by exposing the DUT to a heavy ion beam. Potential Single Event Latch-up (SEL) was checked throughout heavy-ion testing by monitoring device current