Designing Testability Into An Existing Microprocessor Board

Master of ScienceDepartment of Electrical and Computer EngineeringThis thesis presents the hardware implementation of a microprocessor system built according to the microprocessor-controlled Built-In Self-Test (BIST) techniques as presented by Gordon [Gordon 1991 a]. It covers issues relating to the isolation of the edge connector and secondary board areas, to the use and function of a fieldprogrammable gate array (Logic Cell Array)n", to the implementation of electronic wraparounds, and to the general design of the software to support the testability features. In addition, it covers the general use of the ANSI/IEEE Std. 1149.1 test bus for diagnosis, isolation, and board-level partitioning

Run-time reconfigurable, fault-tolerant FPGA systems for space applications

Cozzi D. Run-time reconfigurable, fault-tolerant FPGA systems for space applications. Bielefeld: Universität Bielefeld; 2016.The aim of this thesis is to investigate the use of Dynamic Partial Reconfiguration (DPR) on Commercial Off-the-Shelf (COTS) FPGAs in space applications. Reconfigurable systems gained interest in a wide range of application fields, including aerospace, where electronic devices are exposed to a harsh working environment. COTS SRAM-based FPGA devices represent an interesting hardware platform for this kind of systems since they combine low cost with the possibility to utilize state-of-the-art processing power as well as the flexibility of reconfigurable hardware. FPGA architectures have high computational power and thanks to their ability to be reconfigured at run-time, they became interesting candidates for payload processing in space applications. The presented Dynamic Reconfigurable Processing Module (DRPM) has been developed to investigate the use of the DPR approach for satellite payload processing. This scalable platform combines dynamically reconfigurable FPGAs with the required avionic interfaces (e.g., SpaceWire, MIL-STD-1553B, and SpaceFibre). In particular, a novel communication interface has been developed, the Heterogeneous Multi Processor Communication Interface (HMPCI), which allows inter-process communication with small latency and low memory footprint. Current synthesis tools do not support fully the DPR capabilities of FPGAs. Therefore, this thesis introduces INDRA 2.0: an INtegrated Design flow for Reconfigurable Architectures. The key part of INDRA 2.0 is DHHarMa: a Design flow for Homogeneous Hard Macros, which generates homogeneous hard macros for Xilinx FPGAs starting from a high-level description (e.g., VHDL). In particular, the homogeneous DHHarMa router is explained in detail, providing novel terminologies and algorithms, which have enabled the generation of homogeneous routed designs. Results have been shown that Design flow for Homogeneous Hard Macros (DHHarMa) can route homogeneously a communication infrastructure utilizing just between 1% and 31% more resources than the Xilinx router, which cannot provide a homogeneous solution. Furthermore, the permanent faults that can occur on FPGAs have been investigated. This thesis presents OLT(RE)2: an on-line on-demand approach to testing permanent faults induced by radiation in reconfigurable systems used in space missions. The proposed approach relies on a test circuit and custom placer and router. OLT(RE)2 exploits DPR to place the test circuits at run-time. Its goal is to test unprogrammed areas of the FPGA before using them. Experimental results of OLT(RE)2 have shown that is possible to generate, place, and route the test circuits needed to detect on average more than 99 % of the physical wires and on average about 97 % of the programmable interconnection points of a large arbitrary region of the FPGA in a reasonable time. Moreover, the test can be run on the target device without interfering the functional behavior of the system

Connecting the World of Embedded Mobiles: The RIOT Approach to Ubiquitous Networking for the Internet of Things

The Internet of Things (IoT) is rapidly evolving based on low-power compliant protocol standards that extend the Internet into the embedded world. Pioneering implementations have proven it is feasible to inter-network very constrained devices, but had to rely on peculiar cross-layered designs and offer a minimalistic set of features. In the long run, however, professional use and massive deployment of IoT devices require full-featured, cleanly composed, and flexible network stacks. This paper introduces the networking architecture that turns RIOT into a powerful IoT system, to enable low-power wireless scenarios. RIOT networking offers (i) a modular architecture with generic interfaces for plugging in drivers, protocols, or entire stacks, (ii) support for multiple heterogeneous interfaces and stacks that can concurrently operate, and (iii) GNRC, its cleanly layered, recursively composed default network stack. We contribute an in-depth analysis of the communication performance and resource efficiency of RIOT, both on a micro-benchmarking level as well as by comparing IoT communication across different platforms. Our findings show that, though it is based on significantly different design trade-offs, the networking subsystem of RIOT achieves a performance equivalent to that of Contiki and TinyOS, the two operating systems which pioneered IoT software platforms

FPGA based Ethernet media level tester

Ethernet is a mature technology with wide usage area in devices communicating with each other. Internet of Things is constantly increasing the number of devices in the world-wide network. Security of aspects of these devices should be considered carefully, creating the need to test devices on Ethernet level. This thesis presents design and implementation of a test device functioning on media level of Ethernet. By modifying, injecting and monitoring Ethernet frames transmitted on the communication media, the functionality of a device under testing can be debugged and tested in different situations. The test device is a multi-purpose communication tester, providing several possible usage areas, but is originally developed for debugging and testing purposes for a custom communication protocol used in Ethernet based automation system. At the time of writing this, the tester is already in use as a part of other test equipment of the automation system. The tester is implemented using existing automation device, consisting four Ethernet ports and an FPGA chip. All functionality is implemented on FPGA, making the implementation work on the hardware level. This brings new possibilities compared to testing Ethernet devices with multifunctional processor based design. The tester is to be connected to the communication media between the tested devices. In a normal situation, the tester device is routing unmodified frames through it with only insignificant delays, making it invisible to surrounding devices. However, based on user commands, frames can be modified runtime or inject new frames to inputs of a device under testing. There are some related commercial Ethernet testing devices already on the market. However, those are found to be expensive and does not provide similar features for frame modifying than the device introduced here. Main drivers for the project was to develop low cost or free testing and monitoring device with the possibility to update the features based on needs found in future. The thesis presents basics of Ethernet with two lowest OSI-layers, functional principles of FPGA chips and other needed aspects on theory level. The theory is then followed by introducing functionalities, design, and implementation of the device. Afterwards, we take a look at the actual tests, how those function and observations noticed during testing. Lastly, we summarize briefly the thesis and consider the possible future development of the project

Energy Efficient and High Density Integrated Photonic Transceivers

Light, as a medium for communication, has the unique ability to transmit volumes of data with minimal energy loss. This capability not only sparked the revolution of internet-based communication over fiber optic networks, but also holds the potential to expand computing beyond our current capabilities. At present, data is stored densely in computer chips, but is sent out of the chip through centimeter-long electrical wires in a slow and energy-intensive process, before finally interfacing with optical transmitters. To bypass this bottleneck, electrical channels can be condensed and converted into light over a compact area using integrated photonic chips. In particular, the silicon photonics technology platform offers the potential for extremely dense data communications due to its high confinement waveguides and compact micro-resonators. However, three major obstacles stand in the way of realizing a low-energy and bandwidth-dense implementation of this technology: the integration of photonics with electronics, optical coupling from the photonic chip to fiber, and scaling up link architectures to multiplex data streams onto many wavelengths. The work in this thesis aims to confront these three challenges and advance integrated photonics technology to unprecedented bandwidth densities and energy efficiencies, with a focus on the first challenge of photonic-electronic integration. It begins with an overview of the escalating demand for inter-chip bandwidths and the potential solution offered by integrated photonics. Next, this thesis builds a theoretical framework for the performance parameters and sources of energy consumption that are addressed in the subsequent sections. After this introductory context, the thesis describes the achievement of the highest density and largest scale photonic-electronic integration to date, using a dense, 25 um pitch 3D bonding process. An 80-channel array fabricated in this integration records the lowest data link energies to date, at 120 fJ/bit, and transfers data at 10 Gbit/s/channel for a record 5.3 Tbit/s/mm2 bandwidth density. The discussion then shifts to the issue of chip-to-fiber coupling efficiency, traditionally the greatest source of loss in photonic links. A substrate-removed edge coupler design reduces this loss to a mere 1.1 dB, and an inverse-designed edge coupler taper shows a fourfold length reduction compared to linear tapers. Lastly, the thesis presents designs for wavelength scaling that increase the number of energy efficient channels on a single fiber. Specifically, it demonstrates a multi-channel, polarization diverse micro-comb receiver and a 3D-integrated transceiver with wavelength interleaving to waveguide buses of cascaded resonators. This thesis builds on photonic device developments to introduce photonic systems with the lowest energy and densest data communications to date. Together, these results unlock the tremendous potential of light as a fast and energy-efficient communication medium between chips, paving a sustainable path towards scaling artificial intelligence and disaggregating computation and memory resources

Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

High-speed, low cost test platform using FPGA technology

The object of this research is to develop a low-cost, adaptable testing platform for multi-GHz digital applications, with concentration on the test requirement of advanced devices. Since most advanced ATEs are very expensive, this equipment is not always available for testing cost-sensitive devices. The approach is to use recently-introduced advanced FPGAs for the core logic of the testing platform, thereby allowing for a low-cost, low power-consumption, high-performance, and adaptable test system. Furthermore to customize the testing system for specific applications, we implemented multiple extension testing modules base on this platform. With these extension modules, new functions can be added easily and the test system can be upgraded with specific features required for other testing purposes. The applications of this platform can help those digital devices to be delivered into market with shorter time, lower cost and help the development of the whole industry.Ph.D