Testable Design and Testing of High-Speed Superconductor Microelectronics

True software-defined radio cellular base stations require extremely fast data converters, which can not currently be implemented in semiconductor technology. Superconductor niobium-based delta ADCs have shown to be able to perform this task. The problem of testing these devices is a severe task, as very little is known about possible defects in this technology. This paper shows an approach for gaining information on these defects and illustrates how BIST can be a solution of detecting defects in ADCs under extreme conditions

Towards Structural Testing of Superconductor Electronics

Many of the semiconductor technologies are already\ud facing limitations while new-generation data and\ud telecommunication systems are implemented. Although in\ud its infancy, superconductor electronics (SCE) is capable of\ud handling some of these high-end tasks. We have started a\ud defect-oriented test methodology for SCE, so that reliable\ud systems can be implemented in this technology. In this\ud paper, the details of the study on the Rapid Single-Flux\ud Quantum (RSFQ) process are presented. We present\ud common defects in the SCE processes and corresponding\ud test methodologies to detect them. The (measurement)\ud results prove that we are able to detect possible random\ud defects for statistical purposes in yield analysis. This\ud paper also presents possible test methodologies for RSFQ\ud circuits based on defect oriented testing (DOT)

Testability issues in superconductor electronics

An emerging technology for solutions in high-end applications in computing and telecommunication is superconductor electronics. A system-level study has been carried out to verify the feasibility of DfT in superconductor electronics. In this paper, we present how this can be realized to monitor so-called single-flux quantum pulses. As a part of our research, test structures have been developed to detect structural defects in this technology. We also show detailed test results of those structures. It proves that it is possible to detect possible random defects and provide defect statistics for the Niobium-based fabrication process

Defect-based testing of LTS digital circuits

A Defect-Based Test (DBT) methodology for Superconductor Electronics (SCE) is presented in this thesis, so that commercial production and efficient testing of systems can be implemented in this technology in the future. In the first chapter, the features and prospects for SCE have been presented. The motivation for this research and the outline of the thesis were also described in Chapter 1. It has been shown that high-end applications such as Software-Defined Radio (SDR) and petaflop computers which are extremely difficult to implement in top-of-the-art semiconductor technologies can be realised using SCE. But, a systematic structural test methodology had yet to be developed for SCE and has been addressed in this thesis. A detailed introduction to Rapid Single-Flux Quantum (RSFQ) circuits was presented in Chapter 2. A Josephson Junction (JJ) was described with associated theory behind its operation. The JJ model used in the simulator used in this research work was also presented. RSFQ logic with logic protocols as well as the design and implementation of an example D-type flip-flop (DFF) was also introduced. Finally, advantages and disadvantages of RSFQ circuits have been discussed with focus on the latest developments in the field. Various techniques for testing RSFQ circuits were discussed in Chapter 3. A Process Defect Monitor (PDM) approach was presented for fabrication process analysis. The presented defect-monitor structures were used to gather measurement data, to find the probability of the occurrence of defects in the process which forms the first step for Inductive Fault Analysis (IFA). Results from measurements on these structures were used to create a database for defects. This information can be used as input for performing IFA. "Defect-sprinkling" over a fault-free circuit can be carried out according to the measured defect densities over various layers. After layout extraction and extensive fault simulation, the resulting information will indicate realistic faults. In addition, possible Design-for-Testability (DfT) schemes for monitoring Single-Flux Quantum (SFQ) pulses within an RSFQ circuit has also been discussed in Chapter 3. The requirement for a DfT scheme is inevitable for RSFQ circuits because of their very high frequency of operation and very low operating temperature. It was demonstrated how SFQ pulses can be monitored at an internal node of an SCE circuit, introducing observability using Test-Point Insertion (TPI). Various techniques were discussed for the introduction of DfT and to avoid the delay introduced by the DfT structure if it is required. The available features in the proposed design for customising the detector make it attractive for a detailed DBT of RSFQ circuits. The control of internal nodes has also been illustrated using TPI. The test structures that were designed and implemented to determine the occurrence of defects in the processes can also be used to locate the position for the insertion of the above mentioned DfT structures

Interim research assessment 2003-2005 - Computer Science

This report primarily serves as a source of information for the 2007 Interim Research Assessment Committee for Computer Science at the three technical universities in the Netherlands. The report also provides information for others interested in our research activities

1997 Graduate Student Researchers Program

In 1980, NASA initiated the Graduate Student Research Program (GSRP) to cultivate additional research ties to the academic community and to support a culturally diverse group of students pursuing advanced degrees in science and engineering. Eligibility requirements for this program are described, and program administrators are listed. Research areas are detailed for NASA Headquarters and all Research and Flight Centers

Rapid single flux quantum very large scale integration

Thesis (MScEng)--University of Stellenbosch, 2002.ENGLISH ABSTRACT: Very Large Scale Integration (VLSI) of the Rapid Single Flux Quantum (RSFQ) superconducting logic family is researched. Insight into the design methodologies used for large-scale digital systems and related logistics are reviewed. A brief overview of basic RSFQ logic gates with in mind their application in a cell based layout scheme suited for RSFQ is given. A standard cell model is then proposed, incorporating these cells, on which, a library of low temperature superconducting (L TS) cells are laid out. Research is made into computer techniques for storing and manipulating large-scale circuit netlists. On this base, a method of technology mapping Boolean circuits to an RSFQ equivalent is achieved. Placements on-chip are made, optimized for minimum net length, routed and exported to a popular electronic mask format. Finally, the convergent technology fields of solid state cooling and high-temperature superconducting electronics (HTS) are investigated. This leads to a proposal for a low profile, low cost, HTS cryopackaging concept.AFRIKAANSE OPSOMMING: Grootskaalse integrasie (VLSI) van die "Rapid Single Flux Quantum" (RSFQ) supergeleidende familie van logiese hekke word uiteengesit. Insig in die ontwerpmetodes vir grootskaaIse digitale stelsels en verwante aspekte word ondersoek. 'n Kort oorsig van basiese RSFQ logiese hekke word gegee, met hulle toepassing in 'n uitlegskema wat geskik is vir RSFQ. 'n Standaard sel model, wat bogenoemde selle insluit, word voorgestel en 'n selbiblioteek word uitgele vir lae temperatuur supergeleidende bane. Ondersoek word ingestel na die manipulasie van die beskrywing van elektroniese bane en 'n manier om logiese Boolese baanbeskrywings om te skakel na fisiese RSFQ bane. Die fisiese plasing van selle word bespreek ten einde die verbindingslengte tussen selle te minimeer. Die finale uitleg word omgeskakel na 'n staandaard elektroniese formaat vir baanuitlegte. Die konvergerende tegnologievelde van "soliede toestand" verkoeling en hoe-temperatuur supergeleidende elektroniese bane word bespreek. Ten slotte word 'n nuwe tipe, lae profiel en lae koste kriogeniese verpakking voorgestel