80 research outputs found
Transient error mitigation by means of approximate logic circuits
Mención Internacional en el título de doctorThe technological advances in the manufacturing of electronic circuits have allowed to
greatly improve their performance, but they have also increased the sensitivity of electronic
devices to radiation-induced errors. Among them, the most common effects are
the SEEs, i.e., electrical perturbations provoked by the strike of high-energy particles,
which may modify the internal state of a memory element (SEU) or generate erroneous
transient pulses (SET), among other effects. These events pose a threat for the reliability
of electronic circuits, and therefore fault-tolerance techniques must be applied to
deal with them.
The most common fault-tolerance techniques are based in full replication (DWC or
TMR). These techniques are able to cover a wide range of failure mechanisms present
in electronic circuits. However, they suffer from high overheads in terms of area and
power consumption. For this reason, lighter alternatives are often sought at the expense
of slightly reducing reliability for the least critical circuit sections. In this context a new
paradigm of electronic design is emerging, known as approximate computing, which
is based on improving the circuit performance in change of slight modifications of the
intended functionality. This is an interesting approach for the design of lightweight
fault-tolerant solutions, which has not been yet studied in depth.
The main goal of this thesis consists in developing new lightweight fault-tolerant
techniques with partial replication, by means of approximate logic circuits. These
circuits can be designed with great flexibility. This way, the level of protection as
well as the overheads can be adjusted at will depending on the necessities of each
application. However, finding optimal approximate circuits for a given application is
still a challenge.
In this thesis a method for approximate circuit generation is proposed, denoted
as fault approximation, which consists in assigning constant logic values to specific
circuit lines. On the other hand, several criteria are developed to generate the most
suitable approximate circuits for each application, by using this fault approximation
mechanism. These criteria are based on the idea of approximating the least testable
sections of circuits, which allows reducing overheads while minimising the loss of reliability.
Therefore, in this thesis the selection of approximations is linked to testability
measures.
The first criterion for fault selection developed in this thesis uses static testability
measures. The approximations are generated from the results of a fault simulation of
the target circuit, and from a user-specified testability threshold. The amount of approximated
faults depends on the chosen threshold, which allows to generate approximate circuits with different performances. Although this approach was initially intended for
combinational circuits, an extension to sequential circuits has been performed as well,
by considering the flip-flops as both inputs and outputs of the combinational part of
the circuit. The experimental results show that this technique achieves a wide scalability,
and an acceptable trade-off between reliability versus overheads. In addition, its
computational complexity is very low.
However, the selection criterion based in static testability measures has some drawbacks.
Adjusting the performance of the generated approximate circuits by means of
the approximation threshold is not intuitive, and the static testability measures do not
take into account the changes as long as faults are approximated. Therefore, an alternative
criterion is proposed, which is based on dynamic testability measures. With this
criterion, the testability of each fault is computed by means of an implication-based
probability analysis. The probabilities are updated with each new approximated fault,
in such a way that on each iteration the most beneficial approximation is chosen, that
is, the fault with the lowest probability. In addition, the computed probabilities allow
to estimate the level of protection against faults that the generated approximate circuits
provide. Therefore, it is possible to generate circuits which stick to a target error rate.
By modifying this target, circuits with different performances can be obtained. The
experimental results show that this new approach is able to stick to the target error rate
with reasonably good precision. In addition, the approximate circuits generated with
this technique show better performance than with the approach based in static testability
measures. In addition, the fault implications have been reused too in order to
implement a new type of logic transformation, which consists in substituting functionally
similar nodes.
Once the fault selection criteria have been developed, they are applied to different
scenarios. First, an extension of the proposed techniques to FPGAs is performed,
taking into account the particularities of this kind of circuits. This approach has been
validated by means of radiation experiments, which show that a partial replication with
approximate circuits can be even more robust than a full replication approach, because
a smaller area reduces the probability of SEE occurrence. Besides, the proposed
techniques have been applied to a real application circuit as well, in particular to the
microprocessor ARM Cortex M0. A set of software benchmarks is used to generate
the required testability measures. Finally, a comparative study of the proposed approaches
with approximate circuit generation by means of evolutive techniques have
been performed. These approaches make use of a high computational capacity to generate
multiple circuits by trial-and-error, thus reducing the possibility of falling into
local minima. The experimental results demonstrate that the circuits generated with
evolutive approaches are slightly better in performance than the circuits generated with
the techniques here proposed, although with a much higher computational effort.
In summary, several original fault mitigation techniques with approximate logic
circuits are proposed. These approaches are demonstrated in various scenarios, showing
that the scalability and adaptability to the requirements of each application are their
main virtuesLos avances tecnológicos en la fabricación de circuitos electrónicos han permitido mejorar
en gran medida sus prestaciones, pero también han incrementado la sensibilidad
de los mismos a los errores provocados por la radiación. Entre ellos, los más comunes
son los SEEs, perturbaciones eléctricas causadas por el impacto de partículas de alta
energía, que entre otros efectos pueden modificar el estado de los elementos de memoria
(SEU) o generar pulsos transitorios de valor erróneo (SET). Estos eventos suponen
un riesgo para la fiabilidad de los circuitos electrónicos, por lo que deben ser tratados
mediante técnicas de tolerancia a fallos.
Las técnicas de tolerancia a fallos más comunes se basan en la replicación completa
del circuito (DWC o TMR). Estas técnicas son capaces de cubrir una amplia variedad
de modos de fallo presentes en los circuitos electrónicos. Sin embargo, presentan un
elevado sobrecoste en área y consumo. Por ello, a menudo se buscan alternativas más
ligeras, aunque no tan efectivas, basadas en una replicación parcial. En este contexto
surge una nueva filosofía de diseño electrónico, conocida como computación aproximada,
basada en mejorar las prestaciones de un diseño a cambio de ligeras modificaciones
de la funcionalidad prevista. Es un enfoque atractivo y poco explorado para el diseño
de soluciones ligeras de tolerancia a fallos.
El objetivo de esta tesis consiste en desarrollar nuevas técnicas ligeras de tolerancia
a fallos por replicación parcial, mediante el uso de circuitos lógicos aproximados. Estos
circuitos se pueden diseñar con una gran flexibilidad. De este forma, tanto el nivel de
protección como el sobrecoste se pueden regular libremente en función de los requisitos
de cada aplicación. Sin embargo, encontrar los circuitos aproximados óptimos para
cada aplicación es actualmente un reto.
En la presente tesis se propone un método para generar circuitos aproximados, denominado
aproximación de fallos, consistente en asignar constantes lógicas a ciertas
líneas del circuito. Por otro lado, se desarrollan varios criterios de selección para, mediante
este mecanismo, generar los circuitos aproximados más adecuados para cada
aplicación. Estos criterios se basan en la idea de aproximar las secciones menos testables
del circuito, lo que permite reducir los sobrecostes minimizando la perdida de
fiabilidad. Por tanto, en esta tesis la selección de aproximaciones se realiza a partir de
medidas de testabilidad.
El primer criterio de selección de fallos desarrollado en la presente tesis hace uso de
medidas de testabilidad estáticas. Las aproximaciones se generan a partir de los resultados
de una simulación de fallos del circuito objetivo, y de un umbral de testabilidad
especificado por el usuario. La cantidad de fallos aproximados depende del umbral escogido, lo que permite generar circuitos aproximados con diferentes prestaciones.
Aunque inicialmente este método ha sido concebido para circuitos combinacionales,
también se ha realizado una extensión a circuitos secuenciales, considerando los biestables
como entradas y salidas de la parte combinacional del circuito. Los resultados
experimentales demuestran que esta técnica consigue una buena escalabilidad, y unas
prestaciones de coste frente a fiabilidad aceptables. Además, tiene un coste computacional
muy bajo.
Sin embargo, el criterio de selección basado en medidas estáticas presenta algunos
inconvenientes. No resulta intuitivo ajustar las prestaciones de los circuitos aproximados
a partir de un umbral de testabilidad, y las medidas estáticas no tienen en cuenta los
cambios producidos a medida que se van aproximando fallos. Por ello, se propone un
criterio alternativo de selección de fallos, basado en medidas de testabilidad dinámicas.
Con este criterio, la testabilidad de cada fallo se calcula mediante un análisis de probabilidades
basado en implicaciones. Las probabilidades se actualizan con cada nuevo
fallo aproximado, de forma que en cada iteración se elige la aproximación más favorable,
es decir, el fallo con menor probabilidad. Además, las probabilidades calculadas
permiten estimar la protección frente a fallos que ofrecen los circuitos aproximados
generados, por lo que es posible generar circuitos que se ajusten a una tasa de fallos
objetivo. Modificando esta tasa se obtienen circuitos aproximados con diferentes prestaciones.
Los resultados experimentales muestran que este método es capaz de ajustarse
razonablemente bien a la tasa de fallos objetivo. Además, los circuitos generados
con esta técnica muestran mejores prestaciones que con el método basado en medidas
estáticas. También se han aprovechado las implicaciones de fallos para implementar
un nuevo tipo de transformación lógica, consistente en sustituir nodos funcionalmente
similares.
Una vez desarrollados los criterios de selección de fallos, se aplican a distintos
campos. En primer lugar, se hace una extensión de las técnicas propuestas para FPGAs,
teniendo en cuenta las particularidades de este tipo de circuitos. Esta técnica se ha validado
mediante experimentos de radiación, los cuales demuestran que una replicación
parcial con circuitos aproximados puede ser incluso más robusta que una replicación
completa, ya que un área más pequeña reduce la probabilidad de SEEs. Por otro lado,
también se han aplicado las técnicas propuestas en esta tesis a un circuito de aplicación
real, el microprocesador ARM Cortex M0, utilizando un conjunto de benchmarks
software para generar las medidas de testabilidad necesarias. Por ´último, se realiza un
estudio comparativo de las técnicas desarrolladas con la generación de circuitos aproximados
mediante técnicas evolutivas. Estas técnicas hacen uso de una gran capacidad
de cálculo para generar múltiples circuitos mediante ensayo y error, reduciendo la posibilidad
de caer en algún mínimo local. Los resultados confirman que, en efecto, los
circuitos generados mediante técnicas evolutivas son ligeramente mejores en prestaciones
que con las técnicas aquí propuestas, pero con un coste computacional mucho
mayor.
En definitiva, se proponen varias técnicas originales de mitigación de fallos mediante
circuitos aproximados. Se demuestra que estas técnicas tienen diversas aplicaciones,
haciendo de la flexibilidad y adaptabilidad a los requisitos de cada aplicación
sus principales virtudes.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Raoul Velazco.- Secretario: Almudena Lindoso Muñoz.- Vocal: Jaume Segura Fuste
Logic synthesis and testing techniques for switching nano-crossbar arrays
Beyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements logic, arithmetic, and memory elements by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of logic, arithmetic, and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of â\u80\u9cEmerging Computing Modelsâ\u80\u9d or â\u80\u9cComputational Nanoelectronicsâ\u80\u9d, more specifically the design, modeling, and simulation of new nanoscale switches beyond CMOS
Algorithms for Power Aware Testing of Nanometer Digital ICs
At-speed testing of deep-submicron digital very large scale integrated (VLSI) circuits
has become mandatory to catch small delay defects. Now, due to continuous shrinking
of complementary metal oxide semiconductor (CMOS) transistor feature size, power
density grows geometrically with technology scaling. Additionally, power dissipation
inside a digital circuit during the testing phase (for test vectors under all fault models
(Potluri, 2015)) is several times higher than its power dissipation during the normal
functional phase of operation. Due to this, the currents that flow in the power grid during
the testing phase, are much higher than what the power grid is designed for (the
functional phase of operation). As a result, during at-speed testing, the supply grid
experiences unacceptable supply IR-drop, ultimately leading to delay failures during
at-speed testing. Since these failures are specific to testing and do not occur during
functional phase of operation of the chip, these failures are usually referred to false
failures, and they reduce the yield of the chip, which is undesirable.
In nanometer regime, process parameter variations has become a major problem.
Due to the variation in signalling delays caused by these variations, it is important to
perform at-speed testing even for stuck faults, to reduce the test escapes (McCluskey
and Tseng, 2000; Vorisek et al., 2004). In this context, the problem of excessive peak
power dissipation causing false failures, that was addressed previously in the context of
at-speed transition fault testing (Saxena et al., 2003; Devanathan et al., 2007a,b,c), also
becomes prominent in the context of at-speed testing of stuck faults (Maxwell et al.,
1996; McCluskey and Tseng, 2000; Vorisek et al., 2004; Prabhu and Abraham, 2012;
Potluri, 2015; Potluri et al., 2015). It is well known that excessive supply IR-drop during
at-speed testing can be kept under control by minimizing switching activity during
testing (Saxena et al., 2003). There is a rich collection of techniques proposed in the past
for reduction of peak switching activity during at-speed testing of transition/delay faults
ii
in both combinational and sequential circuits. As far as at-speed testing of stuck faults
are concerned, while there were some techniques proposed in the past for combinational
circuits (Girard et al., 1998; Dabholkar et al., 1998), there are no techniques concerning
the same for sequential circuits. This thesis addresses this open problem. We
propose algorithms for minimization of peak switching activity during at-speed testing
of stuck faults in sequential digital circuits under the combinational state preservation
scan (CSP-scan) architecture (Potluri, 2015; Potluri et al., 2015). First, we show that,
under this CSP-scan architecture, when the test set is completely specified, the peak
switching activity during testing can be minimized by solving the Bottleneck Traveling
Salesman Problem (BTSP). This mapping of peak test switching activity minimization
problem to BTSP is novel, and proposed for the first time in the literature.
Usually, as circuit size increases, the percentage of don’t cares in the test set increases.
As a result, test vector ordering for any arbitrary filling of don’t care bits
is insufficient for producing effective reduction in switching activity during testing of
large circuits. Since don’t cares dominate the test sets for larger circuits, don’t care
filling plays a crucial role in reducing switching activity during testing. Taking this
into consideration, we propose an algorithm, XStat, which is capable of performing test
vector ordering while preserving don’t care bits in the test vectors, following which, the
don’t cares are filled in an intelligent fashion for minimizing input switching activity,
which effectively minimizes switching activity inside the circuit (Girard et al., 1998).
Through empirical validation on benchmark circuits, we show that XStat minimizes
peak switching activity significantly, during testing.
Although XStat is a very powerful heuristic for minimizing peak input-switchingactivity,
it will not guarantee optimality. To address this issue, we propose an algorithm
that uses Dynamic Programming to calculate the lower bound for a given sequence
of test vectors, and subsequently uses a greedy strategy for filling don’t cares in this
sequence to achieve this lower bound, thereby guaranteeing optimality. This algorithm,
which we refer to as DP-fill in this thesis, provides the globally optimal solution for
minimizing peak input-switching-activity and also is the best known in the literature
for minimizing peak input-switching-activity during testing. The proof of optimality of
DP-fill in minimizing peak input-switching-activity is also provided in this thesis
Applying patterns in embedded systems design for managing quality attributes and their trade-offs
Embedded systems comprise one of the most important types of software-intensive systems, as they are pervasive and used in daily life more than any other type, e.g., in cars or in electrical appliances. When these systems operate under hard constraints, the violation of which can lead to catastrophic events, the system is classified as a critical embedded system (CES). The quality attributes related to these hard constraints are named critical quality attributes (CQAs). For example, the performance of the software for cruise-control or self-driving in a car are critical as they can potentially relate to harming human lives. Despite the growing body of knowledge on engineering CESs, there is still a lack of approaches that can support its design, while managing CQAs and their trade-offs with noncritical ones (e.g., maintainability and reusability). To address this gap, the state-of-research and practice on designing CES and managing quality trade-offs were explored, approaches to improve its design identified, and the merit of these approaches empirically investigated. When designing software, one common approach is to organize its components according to well-known structures, named design patterns. However, these patterns may be avoided in some classes of systems such as CES, as they are sometimes associated with the detriment of CQAs. In short, the findings reported in the thesis suggest that, when applicable, design patterns can promote CQAs while supporting the management of trade-offs. The thesis also reports on a phenomena, namely pattern grime, and factors that can influence the extent of the observed benefits
Dagstuhl News January - December 2007
"Dagstuhl News" is a publication edited especially for the members of the Foundation "Informatikzentrum Schloss Dagstuhl" to thank them for their support. The News give a summary of the scientific work being done in Dagstuhl. Each Dagstuhl Seminar is presented by a small abstract describing the contents and scientific highlights of the seminar as well as the perspectives or challenges of the research topic
Combining SOA and BPM Technologies for Cross-System Process Automation
This paper summarizes the results of an industry case study that introduced a cross-system business process automation solution based on a combination of SOA and BPM standard technologies (i.e., BPMN, BPEL, WSDL). Besides discussing major weaknesses of the existing, custom-built, solution and comparing them against experiences with the developed prototype, the paper presents a course of action for transforming the current solution into the proposed solution. This includes a general approach, consisting of four distinct steps, as well as specific action items that are to be performed for every step. The discussion also covers language and tool support and challenges arising from the transformation
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