Multiprocessor system design tutor : expert system approach

To increase computational bandwidth and system resilience, integration of several microprocessors in a single system becomes necessary. The overall throughput and efficiency of such a system is directly dependent on the hardware and software interconnection supported by the basic microprocessor chip. Sometimes it becomes difficult to put together all the information for design criteria and all the design related formulas. The approach made here is to continuously update the hardware and software information in the database related to a given microprocessor. This information can be accessed at any time for efficient design solution. Intel 80386 and Motorola 68020 microprocessors are reviewed in detail and all the information is stored in a database. The above approach has been implemented in the Multiprocessor System Design - Tutor (MSDT) using the Informix relational database management system. MSDT is a menu driven system implemented to help the system design engineers. MSDT stores and maintains information related to multiprocessor system design, which includes multiprocessor system requirements, microprocessor characteristics, the role of microprocessor in multiprocessor system design and interconnection network configurations and their performance factors. This information is presented to the user via the screen building utility of Informix-4GL; the user can also get a hard copy of all the information within the database by running the report generation utility. MSDT also has security password protection. The system has a good help facility available for the design process. At any given time the user can update the data in the table using this menu driven system. The system is intended to grow into a complete evaluation system based on the Informix-4GL. It is developed on the basis of Fourth Generation Language which has a screen building utility, a menu building utility, a report writer and a window manager. This system will suggest the candidate microprocessor and suitable support chips and interconnection techniques for different applications

Integration of tools for the Design and Assessment of High-Performance, Highly Reliable Computing Systems (DAHPHRS), phase 1

Systems for Space Defense Initiative (SDI) space applications typically require both high performance and very high reliability. These requirements present the systems engineer evaluating such systems with the extremely difficult problem of conducting performance and reliability trade-offs over large design spaces. A controlled development process supported by appropriate automated tools must be used to assure that the system will meet design objectives. This report describes an investigation of methods, tools, and techniques necessary to support performance and reliability modeling for SDI systems development. Models of the JPL Hypercubes, the Encore Multimax, and the C.S. Draper Lab Fault-Tolerant Parallel Processor (FTPP) parallel-computing architectures using candidate SDI weapons-to-target assignment algorithms as workloads were built and analyzed as a means of identifying the necessary system models, how the models interact, and what experiments and analyses should be performed. As a result of this effort, weaknesses in the existing methods and tools were revealed and capabilities that will be required for both individual tools and an integrated toolset were identified

Testability and redundancy techniques for improved yield and reliability of CMOS VLSI circuits

The research presented in this thesis is concerned with the design of fault-tolerant integrated circuits as a contribution to the design of fault-tolerant systems. The economical manufacture of very large area ICs will necessitate the incorporation of fault-tolerance features which are routinely employed in current high density dynamic random access memories. Furthermore, the growing use of ICs in safety-critical applications and/or hostile environments in addition to the prospect of single-chip systems will mandate the use of fault-tolerance for improved reliability. A fault-tolerant IC must be able to detect and correct all possible faults that may affect its operation. The ability of a chip to detect its own faults is not only necessary for fault-tolerance, but it is also regarded as the ultimate solution to the problem of testing. Off-line periodic testing is selected for this research because it achieves better coverage of physical faults and it requires less extra hardware than on-line error detection techniques. Tests for CMOS stuck-open faults are shown to detect all other faults. Simple test sequence generation procedures for the detection of all faults are derived. The test sequences generated by these procedures produce a trivial output, thereby, greatly simplifying the task of test response analysis. A further advantage of the proposed test generation procedures is that they do not require the enumeration of faults. The implementation of built-in self-test is considered and it is shown that the hardware overhead is comparable to that associated with pseudo-random and pseudo-exhaustive techniques while achieving a much higher fault coverage through-the use of the proposed test generation procedures. The consideration of the problem of testing the test circuitry led to the conclusion that complete test coverage may be achieved if separate chips cooperate in testing each other's untested parts. An alternative approach towards complete test coverage would be to design the test circuitry so that it is as distributed as possible and so that it is tested as it performs its function. Fault correction relies on the provision of spare units and a means of reconfiguring the circuit so that the faulty units are discarded. This raises the question of what is the optimum size of a unit? A mathematical model, linking yield and reliability is therefore developed to answer such a question and also to study the effects of such parameters as the amount of redundancy, the size of the additional circuitry required for testing and reconfiguration, and the effect of periodic testing on reliability. The stringent requirement on the size of the reconfiguration logic is illustrated by the application of the model to a typical example. Another important result concerns the effect of periodic testing on reliability. It is shown that periodic off-line testing can achieve approximately the same level of reliability as on-line testing, even when the time between tests is many hundreds of hours

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

Reusable Reentry Satellite (RRS) system design study

The Reusable Reentry Satellite (RRS) is intended to provide investigators in several biological disciplines with a relatively inexpensive method to access space for up to 60 days with eventual recovery on Earth. The RRS will permit totally intact, relatively soft, recovery of the vehicle, system refurbishment, and reflight with new and varied payloads. The RRS is to be capable of three reflights per year over a 10-year program lifetime. The RRS vehicle will have a large and readily accessible volume near the vehicle center of gravity for the Payload Module (PM) containing the experiment hardware. The vehicle is configured to permit the experimenter late access to the PM prior to launch and rapid access following recovery. The RRS will operate in one of two modes: (1) as a free-flying spacecraft in orbit, and will be allowed to drift in attitude to provide an acceleration environment of less than 10(exp -5) g. the acceleration environment during orbital trim maneuvers will be less than 10(exp -3) g; and (2) as an artificial gravity system which spins at controlled rates to provide an artificial gravity of up to 1.5 Earth g. The RRS system will be designed to be rugged, easily maintained, and economically refurbishable for the next flight. Some systems may be designed to be replaced rather than refurbished, if cost effective and capable of meeting the specified turnaround time. The minimum time between recovery and reflight will be approximately 60 days. The PMs will be designed to be relatively autonomous, with experiments that require few commands and limited telemetry. Mass data storage will be accommodated in the PM. The hardware development and implementation phase is currently expected to start in 1991 with a first launch in late 1993

Proceedings of the NASA Conference on Space Telerobotics, volume 2

These proceedings contain papers presented at the NASA Conference on Space Telerobotics held in Pasadena, January 31 to February 2, 1989. The theme of the Conference was man-machine collaboration in space. The Conference provided a forum for researchers and engineers to exchange ideas on the research and development required for application of telerobotics technology to the space systems planned for the 1990s and beyond. The Conference: (1) provided a view of current NASA telerobotic research and development; (2) stimulated technical exchange on man-machine systems, manipulator control, machine sensing, machine intelligence, concurrent computation, and system architectures; and (3) identified important unsolved problems of current interest which can be dealt with by future research

Proceedings of the First NASA Formal Methods Symposium

Topics covered include: Model Checking - My 27-Year Quest to Overcome the State Explosion Problem; Applying Formal Methods to NASA Projects: Transition from Research to Practice; TLA+: Whence, Wherefore, and Whither; Formal Methods Applications in Air Transportation; Theorem Proving in Intel Hardware Design; Building a Formal Model of a Human-Interactive System: Insights into the Integration of Formal Methods and Human Factors Engineering; Model Checking for Autonomic Systems Specified with ASSL; A Game-Theoretic Approach to Branching Time Abstract-Check-Refine Process; Software Model Checking Without Source Code; Generalized Abstract Symbolic Summaries; A Comparative Study of Randomized Constraint Solvers for Random-Symbolic Testing; Component-Oriented Behavior Extraction for Autonomic System Design; Automated Verification of Design Patterns with LePUS3; A Module Language for Typing by Contracts; From Goal-Oriented Requirements to Event-B Specifications; Introduction of Virtualization Technology to Multi-Process Model Checking; Comparing Techniques for Certified Static Analysis; Towards a Framework for Generating Tests to Satisfy Complex Code Coverage in Java Pathfinder; jFuzz: A Concolic Whitebox Fuzzer for Java; Machine-Checkable Timed CSP; Stochastic Formal Correctness of Numerical Algorithms; Deductive Verification of Cryptographic Software; Coloured Petri Net Refinement Specification and Correctness Proof with Coq; Modeling Guidelines for Code Generation in the Railway Signaling Context; Tactical Synthesis Of Efficient Global Search Algorithms; Towards Co-Engineering Communicating Autonomous Cyber-Physical Systems; and Formal Methods for Automated Diagnosis of Autosub 6000