A Multiproject Chip Approach to the Teaching of Analog MOS LSI and VLSI

Multiproject chip implementation has been used in teaching analog MOS circuit design. After having worked with computer simulation and layout aids in homework problems, students designed novel circuits including several high performance op amps, an A/D converter, a switched capacitor filter, a 1 K dynamic RAM, and a variety of less conventional MOS circuits such as a VII converter, an AC/DC converter, an AM radio receiver, a digitally-controlled analog signal processor, and on-chip circuitry for measuring transistor capacitances. These circuits were laid out as part of an NMOS multiproject chip. Several of the designs exhibit a considerable degree of innovation; fabrication pending, computer simulation shows that some may be pushing the state of the art. Several designs are of interest to digital designers; in fact, the course has provided knowledge and technique needed for detailed digital circuit design at the gate level

A chaotic switched-capacitor circuit for characteristic CMOS noise distributions generation

A switched-capacitor circuit is proposed for the generation of noise resembling the typical noise spectral density of MOS devices. The circuit is based on the combination of two chaotic maps, one generating 1/f noise (hopping map) and the other generating white noise (Bernoulli map). Through a programmable weighted adder stage, the contribution of each map can be controlled and, thereby, the position of the corner frequency. Behavioral models simulations were carried out to prove the correct functionality of the proposed approach.Ministerio de Economía y Competitividad TEC2016-80923-

Hybrid and modular multilevel converter designs for isolated HVDC–DC converters

Efficient medium and high-voltage dc-dc conversion is critical for future dc grids. This paper proposes a hybrid multilevel dc-ac converter structure that is used as the kernel of dc-dc conversion systems. Operation of the proposed dc-ac converter is suited to trapezoidal ac-voltage waveforms. Quantitative and qualitative analyses show that said trapezoidal operation reduces converter footprint, active and passive components' size, and on-state losses relative to conventional modular multilevel converters. The proposed converter is scalable to high voltages with controllable ac-voltage slope; implying tolerable dv/dt stresses on the converter transformer. Structural variations of the proposed converter with enhanced modularity and improved efficiency will be presented and discussed with regards to application in front-to-front isolated dc-dc conversion stages, and in light of said trapezoidal operation. Numerical results provide deeper insight of the presented converter designs with emphasis on system design aspects. Results obtained from a proof-of-concept 1-kW experimental test rig confirm the validity of simulation results, theoretical analyses, and simplified design equations presented in this paper. - 2013 IEEE.Scopu

A BIST solution for frequency domain characterization of analog circuits

This work presents an efficient implementation of a BIST solution for frequency characterization of analog systems. It allows a complete characterization in terms of magnitude and phase, including also harmonic distortion and offset measurements. Signal generation is performed using a modified filter, while response evaluation is based on 1storder ÓÄ modulation and very simple digital processing. The signal generator and the response analyzer have been implemented using the Switched-Capacitor (SC) technique in a standard 0.35ìm-3.3V CMOS technology. Both circuits have been separately validated, and an on-board prototype of the complete test system for frequency characterization has been implemented. Experimental results verify the functionality of the proposed approach, and a dynamic range of [email protected] (1MHz clock) has been demonstrated.Gobierno de España TEC2007-68072/MIC, TSI 020400- 2008-71Catrene European Project 2A105SR

Design considerations for integrated continuous-time chaotic oscillators

This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant hardware nonidealities of Gm-C circuits on the chaotic operation-the basis to design robust integrated circuits with reproducible and easily controllable behavior. The techniques in the paper are illustrated through a circuit fabricated in 2.4-/iin double-poly technology.Comisión Interministerial de Ciencia y Tecnología TIC 96-1392-CO2-

Body bias generator design for ultra-low voltage applications in FDSOI technology

This thesis presents the derivation and validation processes of analytical models describing the dynamic and steady-state behaviors of CC-CP switched capacitor converters. The effects of FDSOI components in the implementation of such circuits is also addressed, studying their impact as compared to ideal models. Finally, the layout of a CMOS CC-CP in 28-nm UTBB-FDSOI technology is designed and tested against predicted functionality