A design representation model for high-level synthesis

Design tools share and exchange various types of information pertaining to the design. The identification of a uniform design representation to capture this information is essential for the development of a successful design environment. We have done an extensive study on the representation needs of existing database tools in the UCI CADLAB; examples of which are graph compilers for high-level hardware specifications, state schedulers, hardware allocators, and microarchitecture optimizers. The result of this study is the development of a design representation model that will serve as a common internal representation (DDM) for all system and behavioral synthesis tools. DDM thus builds the foundation for a CAD Framework in which design tools can communicate via operating on this common representation. The design information is composed of three separate graph models: the conceptual model, the behavioral model and the structural model. The conceptual model (represented by a Design Entity Graph) captures the overall organization of the design information, such as, versions and configurations. The behavioral model (represented by an Augmented Control/Data Flow Graph) describes the design behavior. The structural model (represented by an Annotated Component Graph) captures the hierarchical data path structure and its geometric information. In this paper, we define the last two graph models. They both capture the actual design data of the application domain. Since VHDL has gained increasing popularity as hardware description language for synthesis, we give numerous examples throughout this report that show how the proposed design representation model can be used to represent VHDL specifications

A design tool for high-resolution high-frequency cascade continuous- time Σ∆ modulators

Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, SpainThis paper introduces a CAD methodology to assist the de signer in the implementation of continuous-time (CT) cas- cade Σ∆ modulators. The salient features of this methodology ar e: (a) flexible behavioral modeling for optimum accuracy- efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity; a nd (c) mixed knowledge-based and optimization-based architec- tural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology will be illustrated via the design of a 12 bit 20 MHz CT Σ∆ modulator in a 1.2V 130nm CMOS technology.Ministerio de Ciencia y Educación TEC2004-01752/MICMinisterio de Industria, Turismo y Comercio FIT-330100-2006-134 SPIRIT Projec

Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel

High-level synthesis (HLS) allows hardware designers to think algorithmically and not worry about low-level, cycle-by-cycle details. This provides the ability to quickly explore the architectural design space and tradeoffs between resource utilization and performance. Unfortunately, security evaluation is not a standard part of the HLS design flow. In this article, we aim to understand the effects of memory-based HLS optimizations on power side-channel leakage. We use Xilinx Vivado HLS to develop different cryptographic cores, implement them on a Spartan-6 FPGA, and collect power traces. We evaluate the designs with respect to resource utilization, performance, and information leakage through power consumption. We have two important observations and contributions. First, the choice of resource optimization directive results in different levels of side-channel vulnerabilities. Second, the partitioning optimization directive can greatly compromise the hardware cryptographic system through power side-channel leakage due to the deployment of memory control logic. We describe an evaluation procedure for power side-channel leakage and use it to make best-effort recommendations about how to design more secure architectures in the cryptographic domain

A Critical Review of "Automatic Patch Generation Learned from Human-Written Patches": Essay on the Problem Statement and the Evaluation of Automatic Software Repair

At ICSE'2013, there was the first session ever dedicated to automatic program repair. In this session, Kim et al. presented PAR, a novel template-based approach for fixing Java bugs. We strongly disagree with key points of this paper. Our critical review has two goals. First, we aim at explaining why we disagree with Kim and colleagues and why the reasons behind this disagreement are important for research on automatic software repair in general. Second, we aim at contributing to the field with a clarification of the essential ideas behind automatic software repair. In particular we discuss the main evaluation criteria of automatic software repair: understandability, correctness and completeness. We show that depending on how one sets up the repair scenario, the evaluation goals may be contradictory. Eventually, we discuss the nature of fix acceptability and its relation to the notion of software correctness.Comment: ICSE 2014, India (2014

BDEF : the behavioral design data exchange format

BDDB is a Behavioral Design Data Base that manages the design data produced and consumed by different behavioral synthesis tools. These different design tools retrieve design data from BDDB, manipulate the data, and then store the results back into the data base. BDDB thus needs to address the following two issues: (1) a design data exchange approach and (2) customized design data interfaces. To address the first issue, we have developed a textual description format for describing design data objects and relationships. This language, referred to as the Behavioral Design Data Exchange Format (BDEF), is used as common format for exchanging design data between BDDB and the design tools in the behavioral synthesis environment. To address the second issue, we have developed a behavioral object type description language (generally referred to as schema definition language) for describing the global data structures required by design tools as well as the desired design subviews of this global BDDB design information. One design view class, namely, BDEF, is the topic of this report.In this report we give a formal definition of the BDEF format. Then we describe a comprehensive example of applying BDEF to the behavioral synthesis domain. That is, we present the complete BDEF syntax for the Extended Control/Data Flow Graph Model (ECDFG), which is the design representation model used by most behavioral synthesis tools in the UCI CADLAB synthesis system. We also present several example descriptions of designs using this ECDFG model. A parser/graph compiler from BDEF into the generalized ECDFG design representation as well as a BDEF generator from the ECDFG data structures into the BDEF format have been implemented

Comparing and Combining Lexicase Selection and Novelty Search

Lexicase selection and novelty search, two parent selection methods used in evolutionary computation, emphasize exploring widely in the search space more than traditional methods such as tournament selection. However, lexicase selection is not explicitly driven to select for novelty in the population, and novelty search suffers from lack of direction toward a goal, especially in unconstrained, highly-dimensional spaces. We combine the strengths of lexicase selection and novelty search by creating a novelty score for each test case, and adding those novelty scores to the normal error values used in lexicase selection. We use this new novelty-lexicase selection to solve automatic program synthesis problems, and find it significantly outperforms both novelty search and lexicase selection. Additionally, we find that novelty search has very little success in the problem domain of program synthesis. We explore the effects of each of these methods on population diversity and long-term problem solving performance, and give evidence to support the hypothesis that novelty-lexicase selection resists converging to local optima better than lexicase selection

Silicon compilation

Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory

A Calibrated Time Domain Envelope Measurement System for the Behavioral Modeling of Power Amplifiers

This paper presents a set-up which enables the generation and the calibrated time domain measurements of complex envelopes of modulated signals at both ports of non linear microwave power amplifiers. The architecture of the characterization tool is given. Examples of error corrected time domain envelopes at the input / output RF ports of a 36 dBm output power – 30dB power gain L-band SSPA are shown. Futhermore, the use of this characterization tool and a suitable processing of measurement data are applied to a novel measurement based behavioral modeling approach of non linear devices accounting for memory effects